[PATCH] D50432: [DAGCombiner] Reduce load widths of shifted masks

[Francois Pichet via Phabricator via llvm-commits]

fpichet added a comment.

For example:

given test.ll: 
define dso_local void @swap(i32* %ptr) #0 {
entry:

  %0 = load i32, i32* %ptr, align 4
  %and = and i32 %0, 65280
  %shl = shl i32 %and, 8
  store i32 %shl, i32* %ptr, align 4
  ret void

}

llc -mtriple=armv7-linux-gnu < test.ll
will give:

  ldrb    r1, [r0, #1]
  lsl     r1, r1, #8   // 8
  str     r1, [r0]
  bx      lr

it should be:

  ldrb    r1, [r0, #1]
  lsl     r1, r1, #16  // 16
  str     r1, [r0]
  bx      lr


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D50432/new/

https://reviews.llvm.org/D50432