[PATCH] D53235: [RISCV] Add RV64F codegen support

[Roger Ferrer Ibanez via Phabricator via llvm-commits]

rogfer01 added a comment.

Hi Alex,

then change looks sensible to me but I found there is some sort of issue with the new DAG nodes. Consider the following example (minimised from `CodeGen/Generic/2008-02-25-NegateZero.ll`.

  define void @test(float* %p) {
  entry:
  	%tmp98 = load float, float* %p, align 4
  	call void (i32, ...) @foo( i32 0, float %tmp98 ) nounwind 
  	ret void
  }
  
  declare void @foo(i32, ...)



  $ ./bin/llc -mtriple riscv64 < t.ll

  	.text
  	.file	"<stdin>"
  SoftenFloatOperand Op #0: t21: i64 = RISCVISD::BitcastAndSextF32ToI64 t5
  
  Do not know how to soften this operator's operand!
  UNREACHABLE executed at /home/rferrer/fio/upstream/llvm-src/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp:753!
  Stack dump:
  0.	Program arguments: ./bin/llc -mtriple riscv64 
  1.	Running pass 'Function Pass Manager' on module '<stdin>'.
  2.	Running pass 'RISCV DAG->DAG Pattern Instruction Selection' on function '@test'

I think this happens because `f32` is not legal when no `f` is present, so the type legalizer tries to "soften" it but it doesn't know how to do this.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D53235/new/

https://reviews.llvm.org/D53235