[PATCH] D56201: [LegalizeVectorTypes] Allow single loads and stores for more short vectors

[Jan Vesely via Phabricator via llvm-commits]

jvesely added inline comments.


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Comment at: test/CodeGen/AMDGPU/load-constant-i16.ll:197
-; EG-DAG: 65535
-; EG-DAG: 65535
 define amdgpu_kernel void @constant_zextload_v3i16_to_v3i32(<3 x i32> addrspace(1)* %out, <3 x i16> addrspace(4)* %in) {
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tauril wrote:
> jvesely wrote:
> > is there any reason to remove these lines from the test?
> I removed these lines from the test because the generated code no longer has them in it.
I see. If the values are directly loaded to registers used in STORE_RAW, it'd be nice to preserve the tracking instead of using generic `{{T[0-9]\.[XYZW]}}`
i.e:
`VTX_READ_16 [[ST_LO]].X, ... 0, #1`
`VTX_READ_16 [[ST_LO]].Y, ... 2, #1`
`VTX_READ_16 [[ST_HI]].X, ... 4, #1`


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D56201/new/

https://reviews.llvm.org/D56201