[PATCH] D53235: [RISCV] Add RV64F codegen support

[Alex Bradbury via Phabricator via llvm-commits]

asb updated this revision to Diff 181457.
asb edited reviewers, added: efriedma; removed: eli.friedman.
asb added a comment.

Rebased (no meaningful changes).

I would really, really appreciate a review. I believe this is ready to land and overall a pretty straight-forward patch. The introduction of target-specific nodes to avoid bitcasts to illegal types is used across other backends in LLVM, as well as for RV32D and is pretty straight-forward.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D53235/new/

https://reviews.llvm.org/D53235

Files:
  lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  lib/Target/RISCV/RISCVISelLowering.cpp
  lib/Target/RISCV/RISCVISelLowering.h
  lib/Target/RISCV/RISCVInstrInfoF.td
  test/CodeGen/RISCV/float-arith.ll
  test/CodeGen/RISCV/float-br-fcmp.ll
  test/CodeGen/RISCV/float-convert.ll
  test/CodeGen/RISCV/float-fcmp.ll
  test/CodeGen/RISCV/float-imm.ll
  test/CodeGen/RISCV/float-mem.ll
  test/CodeGen/RISCV/float-select-fcmp.ll
  test/CodeGen/RISCV/rv64f-float-convert.ll

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