[PATCH] D50496: [RISCV] Implment pseudo instructions for load/store from a symbol address.

[Kito Cheng via Phabricator via llvm-commits]

kito-cheng marked an inline comment as done.
kito-cheng added inline comments.


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Comment at: lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:1341
+  MCOperand TmpReg = Inst.getOperand(1);
+  const MCExpr *Symbol = Inst.getOperand(2).getExpr();
+
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jrtc27 wrote:
> Further investigation reveals that, for GNU as, the symbol is still `Operands[1]`, and the temporary register is `Operands[2]`, i.e. `sw a0, foo, t0`.
The order of Operands not literally order in the asm syntax, it's ordered by (outs) (ins) in the pattern, it seems a little counter-intuitive here.


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https://reviews.llvm.org/D50496