[PATCH] D55106: A new software pipliner pass based on non-SSA form

[Masaki Arai via Phabricator via llvm-commits]

masakiarai added a comment.

I think that there is no particular problem in this part itself.

However, I would like to know the plan of how to coexist with MachinePipeliner over the long term.
I believe that the core part of the algorithm is the same and that many codes can be shared with MachinePipeliner.
Also, if both MachinePipeliner and MachineModuloSched are present for a certain period, it is nice to be able to switch both by using them.
For example, I wrote the member function 'AArch64InstrInfo::analyzeLoop' to port MachinePipeliner to AArch64.
Rather than preparing such a function for both passes, I think that it is better to be able to utilize one function with parameter 'bool SSA' in both optimization passes.

I imagine the implementation like RegAlloc* for register allocation passes.
However, this may be difficult because the timing of executing each pass is different.


Repository:
  rL LLVM

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  https://reviews.llvm.org/D55106/new/

https://reviews.llvm.org/D55106