[PATCH] D56520: [WebAssembly] Expand SIMD shifts while V8's implementation disagrees

[Thomas Lively via Phabricator via llvm-commits]

tlively marked an inline comment as done.
tlively added inline comments.


================
Comment at: lib/Target/WebAssembly/WebAssemblyISelLowering.cpp:1164
+                                  .getNode());
+  }
+
----------------
aheejin wrote:
> How is this different from just unrolling this as done in below, like
> ```
> return DAG.UnrollVectorOp(Op.getNode());
> ```
> ?
For example `(i8x16.shl (i8x16.splat (i32.const 1)) 8)` should be equal to a vector of all 1 bytes, since it is shifted by the provided amount modulo the width of a lane. However, if you just naively unroll the shift, you end up with a series of shifts that look like (i32.shl (; lane value ;) 8)`, which shifts modulo 32 instead. The result is you get a vector of all zeroes instead of a vector of all 1 bytes. This code adds an AND instruction before unrolling to explicitly mask the shift amount into the correct range.


Repository:
  rL LLVM

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  https://reviews.llvm.org/D56520/new/

https://reviews.llvm.org/D56520