[PATCH] D56520: [WebAssembly] Expand SIMD shifts while V8's implementation disagrees

[Thomas Lively via Phabricator via llvm-commits]

tlively created this revision.
tlively added reviewers: aheejin, dschuff.
Herald added subscribers: llvm-commits, dmgreen, sunfish, jgravelle-google, sbc100.

V8 currently implements SIMD shifts as taking an immediate operation,
which disagrees with the spec proposal and the toolchain
implementation. As a stopgap measure to get things working, unroll all
vector shifts. Since this is a temporary measure, there are no tests.


Repository:
  rL LLVM

https://reviews.llvm.org/D56520

Files:
  lib/Target/WebAssembly/WebAssemblyISelLowering.cpp


Index: lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
===================================================================
--- lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
+++ lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
@@ -1148,6 +1148,21 @@
   // Only manually lower vector shifts
   assert(Op.getSimpleValueType().isVector());
 
+  // Expand all vector shifts until V8 fixes its implementation
+  // TODO: remove this once V8 is fixed
+  if (!Subtarget->hasUnimplementedSIMD128()) {
+    // Mask the operand
+    SDValue Shift = Op.getOperand(1);
+    uint64_t MaskVal =
+        Op.getSimpleValueType().getVectorElementType().getSizeInBits() - 1;
+    SDValue MaskedShift =
+        DAG.getNode(ISD::AND, DL, Shift.getValueType(), Shift,
+                    DAG.getConstant(MaskVal, DL, Shift.getValueType()));
+    return DAG.UnrollVectorOp(DAG.getNode(Op.getOpcode(), DL, Op.getValueType(),
+                                          Op.getOperand(0), MaskedShift)
+                                  .getNode());
+  }
+
   // Unroll non-splat vector shifts
   BuildVectorSDNode *ShiftVec;
   SDValue SplatVal;


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