[PATCH] D56454: AMDGPU: Adjust the chain for loads writing to the HI part of a register.

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec added a comment.

Can you add a test where low half does not produce a chain? An arithmetic operation and an undef.



================
Comment at: lib/Target/AMDGPU/SIISelLowering.cpp:9027
+
+    SmallVector<SDValue, 4> Ops;
+    for (unsigned I = 0; I < NumOps-1; ++I)
----------------
4 is not enough, it will not be a small vector. I think 16 is ok.


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  https://reviews.llvm.org/D56454/new/

https://reviews.llvm.org/D56454