[PATCH] D55929: Initial AArch64 SLH implementation.

[Kristof Beyls via Phabricator via llvm-commits]

kristof.beyls added inline comments.


================
Comment at: lib/Target/AArch64/AArch64SpeculationHardening.cpp:604
 
-  UseControlFlowSpeculationBarrier = functionUsesHardeningRegister(MF);
+  // Step 1: Enable automatic insertion of SpeculationSafeValue.
+  if (HardenLoads) {
----------------
olista01 wrote:
> Why do you need to insert pseudo-instructions here, only to replace them with ANDs later on? Could this loop be moved to after the control-flow tracking has been inserted, and create the ANDs directly?
This design inserting pseudo-instructions is based on an earlier design I did (which did not get committed) to implement the intrinsics based approach that is also implemented in gcc.
By keeping this design, it will be easier in the future to also support the intrinsics based approach (as documented from a user point-of-view at https://lwn.net/Articles/759423/).
The idea being that the user-specified intrinsics will be lowered to the pseudo-instruction, and that SLH basically inserts the pseudo-instructions. These pseudo-instructions then get lowered in the same way no matter if they came from a user-written intrinsic or from an automatically inserted pseudo-instruction by SLH.
Granted, maybe the only non-trivial part of lowering the pseudo-instruction is the algorithm to optimize/reduce the number of CSDB instructions that are inserted.

Obviously, we could not use the pseudo-instructions for now and only introduce them if we introduce the intrinsics-based approach too.
However, I'm not sure in how far that will complicate the optimization reducing the number of CSDBs inserted.
Let me look into how easy or complicated the alternative design without pseudo-instructions would be.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D55929/new/

https://reviews.llvm.org/D55929