[PATCH] D56264: [RISCV] Add patterns for RV64I SLLW/SRLW/SRAW instructions

[Alex Bradbury via Phabricator via llvm-commits]

asb updated this revision to Diff 180107.
asb added a comment.

Updated to improve pattern definitions. The first patterns were over-constrained, as they would only match shifts where the shift amount operand matched the zexti32 pattern. I introduce the shiftwamt PatFrags so it will match a zexti32 shift amount (and hence avoid generating the unnecessary zero-extend), or a shift amount that isn't zero-extended.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D56264/new/

https://reviews.llvm.org/D56264

Files:
  lib/Target/RISCV/RISCVISelLowering.cpp
  lib/Target/RISCV/RISCVInstrInfo.td
  test/CodeGen/RISCV/alu32.ll
  test/CodeGen/RISCV/alu64.ll
  test/CodeGen/RISCV/rv64i-exhaustive-w-insts.ll

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