[PATCH] D56011: [x86] lower extracted fadd/fsub to horizontal vector math

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


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Comment at: lib/Target/X86/X86ISelLowering.cpp:18339
+  SDValue RHS = Op.getOperand(1);
+  if (!LHS.hasOneUse() || !RHS.hasOneUse() || !Subtarget.hasSSE3())
+    return Op;
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Do both ops have to be one use for this to be useful?


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Comment at: lib/Target/X86/X86ISelLowering.cpp:18358
+    std::swap(LExtIndex, RExtIndex);
+  if (LExtIndex != 0 || RExtIndex != 1)
+    return Op;
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Is it useful to support any suitable neighbouring pairs of extracted values?


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Comment at: lib/Target/X86/X86ISelLowering.cpp:18364
+  unsigned BitWidth = VecVT.getSizeInBits();
+  if (BitWidth != 128 && BitWidth != 256)
+    return Op;
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Is this important? I think its what you were asking about AVX512 (which doesn't have HADDPS). I'd start by adding avx512f/avx512vl tests to haddsub-undef.ll


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D56011/new/

https://reviews.llvm.org/D56011