[PATCH] D49966: [X86] Performing DAG pruning before selection of LEA instructions.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

In D49966#1343225 <https://reviews.llvm.org/D49966#1343225>, @xbolva00 wrote:

> https://godbolt.org/z/0ZOx52


That behavior is intentional. The X86FixupLEAs.cpp pass changed from the gcc/icc code to LEA+ADD because "lea     eax, [rdi+1+rdi]" is a 3 cycle instruction with 1 cycle reciprocal throughput on all Intel Core CPUs from Sandy Bridge to present. "lea eax, [rdi+rdi]" is 1 cycle latency with 0.5 reciprocal throughput. And "add eax, 1" is 1 cycle with a reciprocal throughput of 0.33 or 0.25. So the 2 instructions should be better performing than the single LEA. Though it is bad that -Os doesn't disable this optimization.


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  rL LLVM

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  https://reviews.llvm.org/D49966/new/

https://reviews.llvm.org/D49966