[PATCH] D44528: [PowerPC] Implement canCombineStoreAndExtract and provide the missing codegen patterns

[Nemanja Ivanovic via Phabricator via llvm-commits]

nemanjai abandoned this revision.
nemanjai marked an inline comment as done.
nemanjai added a comment.

Upon closer inspection, this actually almost never fires on PPC so spending any more time on it does not seem useful. Abandoning this patch.



================
Comment at: lib/Target/PowerPC/PPCISelLowering.cpp:14307
+  // Only have combined stores for sub-word types on Power9.
+  if (BitWidth > 32 || (!Subtarget.hasP9Vector() && BitWidth != 32))
+    return false;
----------------
steven.zhang wrote:
> I didn't take deep look at the implementation for this patch. The condition here seems not quite align with the comments. If the bitwidth is 32bit, we will combine the store and extract no matter if it is Power9 or not. I am not sure if this is by intention. 
That is correct. And I feel that the comment does not suggest otherwise. Perhaps if I change the comment to something like:
```
// Prior to Power9, we only have an instruction that combines a store and extract
// for i32 (STXSIWX). ISA 3.0 (Power9) introduced instructions that do this for
// subword types (i8, i16). There is also no advantage to doing this for i64 on
// any subtarget.
```


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  https://reviews.llvm.org/D44528/new/

https://reviews.llvm.org/D44528