[llvm] r350156 - [PowerPC][NFC] Macro for register set defs for the Asm Parser
Nemanja Ivanovic via llvm-commits
llvm-commits at lists.llvm.org
Sat Dec 29 08:13:12 PST 2018
Author: nemanjai
Date: Sat Dec 29 08:13:11 2018
New Revision: 350156
URL: http://llvm.org/viewvc/llvm-project?rev=350156&view=rev
Log:
[PowerPC][NFC] Macro for register set defs for the Asm Parser
We have some unfortunate code in the back end that defines a bunch of register
sets for the Asm Parser. Every time another class is needed in the parser, we
have to add another one of those definitions with explicit lists of registers.
This NFC patch simply provides macros to use to condense that code a little bit.
Differential revision: https://reviews.llvm.org/D54433
Modified:
llvm/trunk/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
llvm/trunk/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h
Modified: llvm/trunk/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp?rev=350156&r1=350155&r2=350156&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp Sat Dec 29 08:13:11 2018
@@ -21,7 +21,6 @@
#include "llvm/MC/MCParser/MCAsmParser.h"
#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
#include "llvm/MC/MCParser/MCTargetAsmParser.h"
-#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCStreamer.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/MC/MCSymbolELF.h"
@@ -31,169 +30,7 @@
using namespace llvm;
-static const MCPhysReg RRegs[32] = {
- PPC::R0, PPC::R1, PPC::R2, PPC::R3,
- PPC::R4, PPC::R5, PPC::R6, PPC::R7,
- PPC::R8, PPC::R9, PPC::R10, PPC::R11,
- PPC::R12, PPC::R13, PPC::R14, PPC::R15,
- PPC::R16, PPC::R17, PPC::R18, PPC::R19,
- PPC::R20, PPC::R21, PPC::R22, PPC::R23,
- PPC::R24, PPC::R25, PPC::R26, PPC::R27,
- PPC::R28, PPC::R29, PPC::R30, PPC::R31
-};
-static const MCPhysReg RRegsNoR0[32] = {
- PPC::ZERO,
- PPC::R1, PPC::R2, PPC::R3,
- PPC::R4, PPC::R5, PPC::R6, PPC::R7,
- PPC::R8, PPC::R9, PPC::R10, PPC::R11,
- PPC::R12, PPC::R13, PPC::R14, PPC::R15,
- PPC::R16, PPC::R17, PPC::R18, PPC::R19,
- PPC::R20, PPC::R21, PPC::R22, PPC::R23,
- PPC::R24, PPC::R25, PPC::R26, PPC::R27,
- PPC::R28, PPC::R29, PPC::R30, PPC::R31
-};
-static const MCPhysReg XRegs[32] = {
- PPC::X0, PPC::X1, PPC::X2, PPC::X3,
- PPC::X4, PPC::X5, PPC::X6, PPC::X7,
- PPC::X8, PPC::X9, PPC::X10, PPC::X11,
- PPC::X12, PPC::X13, PPC::X14, PPC::X15,
- PPC::X16, PPC::X17, PPC::X18, PPC::X19,
- PPC::X20, PPC::X21, PPC::X22, PPC::X23,
- PPC::X24, PPC::X25, PPC::X26, PPC::X27,
- PPC::X28, PPC::X29, PPC::X30, PPC::X31
-};
-static const MCPhysReg XRegsNoX0[32] = {
- PPC::ZERO8,
- PPC::X1, PPC::X2, PPC::X3,
- PPC::X4, PPC::X5, PPC::X6, PPC::X7,
- PPC::X8, PPC::X9, PPC::X10, PPC::X11,
- PPC::X12, PPC::X13, PPC::X14, PPC::X15,
- PPC::X16, PPC::X17, PPC::X18, PPC::X19,
- PPC::X20, PPC::X21, PPC::X22, PPC::X23,
- PPC::X24, PPC::X25, PPC::X26, PPC::X27,
- PPC::X28, PPC::X29, PPC::X30, PPC::X31
-};
-static const MCPhysReg FRegs[32] = {
- PPC::F0, PPC::F1, PPC::F2, PPC::F3,
- PPC::F4, PPC::F5, PPC::F6, PPC::F7,
- PPC::F8, PPC::F9, PPC::F10, PPC::F11,
- PPC::F12, PPC::F13, PPC::F14, PPC::F15,
- PPC::F16, PPC::F17, PPC::F18, PPC::F19,
- PPC::F20, PPC::F21, PPC::F22, PPC::F23,
- PPC::F24, PPC::F25, PPC::F26, PPC::F27,
- PPC::F28, PPC::F29, PPC::F30, PPC::F31
-};
-static const MCPhysReg SPERegs[32] = {
- PPC::S0, PPC::S1, PPC::S2, PPC::S3,
- PPC::S4, PPC::S5, PPC::S6, PPC::S7,
- PPC::S8, PPC::S9, PPC::S10, PPC::S11,
- PPC::S12, PPC::S13, PPC::S14, PPC::S15,
- PPC::S16, PPC::S17, PPC::S18, PPC::S19,
- PPC::S20, PPC::S21, PPC::S22, PPC::S23,
- PPC::S24, PPC::S25, PPC::S26, PPC::S27,
- PPC::S28, PPC::S29, PPC::S30, PPC::S31
-};
-static const MCPhysReg VFRegs[32] = {
- PPC::VF0, PPC::VF1, PPC::VF2, PPC::VF3,
- PPC::VF4, PPC::VF5, PPC::VF6, PPC::VF7,
- PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11,
- PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15,
- PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19,
- PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23,
- PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27,
- PPC::VF28, PPC::VF29, PPC::VF30, PPC::VF31
-};
-static const MCPhysReg VRegs[32] = {
- PPC::V0, PPC::V1, PPC::V2, PPC::V3,
- PPC::V4, PPC::V5, PPC::V6, PPC::V7,
- PPC::V8, PPC::V9, PPC::V10, PPC::V11,
- PPC::V12, PPC::V13, PPC::V14, PPC::V15,
- PPC::V16, PPC::V17, PPC::V18, PPC::V19,
- PPC::V20, PPC::V21, PPC::V22, PPC::V23,
- PPC::V24, PPC::V25, PPC::V26, PPC::V27,
- PPC::V28, PPC::V29, PPC::V30, PPC::V31
-};
-static const MCPhysReg VSRegs[64] = {
- PPC::VSL0, PPC::VSL1, PPC::VSL2, PPC::VSL3,
- PPC::VSL4, PPC::VSL5, PPC::VSL6, PPC::VSL7,
- PPC::VSL8, PPC::VSL9, PPC::VSL10, PPC::VSL11,
- PPC::VSL12, PPC::VSL13, PPC::VSL14, PPC::VSL15,
- PPC::VSL16, PPC::VSL17, PPC::VSL18, PPC::VSL19,
- PPC::VSL20, PPC::VSL21, PPC::VSL22, PPC::VSL23,
- PPC::VSL24, PPC::VSL25, PPC::VSL26, PPC::VSL27,
- PPC::VSL28, PPC::VSL29, PPC::VSL30, PPC::VSL31,
-
- PPC::V0, PPC::V1, PPC::V2, PPC::V3,
- PPC::V4, PPC::V5, PPC::V6, PPC::V7,
- PPC::V8, PPC::V9, PPC::V10, PPC::V11,
- PPC::V12, PPC::V13, PPC::V14, PPC::V15,
- PPC::V16, PPC::V17, PPC::V18, PPC::V19,
- PPC::V20, PPC::V21, PPC::V22, PPC::V23,
- PPC::V24, PPC::V25, PPC::V26, PPC::V27,
- PPC::V28, PPC::V29, PPC::V30, PPC::V31
-};
-static const MCPhysReg VSFRegs[64] = {
- PPC::F0, PPC::F1, PPC::F2, PPC::F3,
- PPC::F4, PPC::F5, PPC::F6, PPC::F7,
- PPC::F8, PPC::F9, PPC::F10, PPC::F11,
- PPC::F12, PPC::F13, PPC::F14, PPC::F15,
- PPC::F16, PPC::F17, PPC::F18, PPC::F19,
- PPC::F20, PPC::F21, PPC::F22, PPC::F23,
- PPC::F24, PPC::F25, PPC::F26, PPC::F27,
- PPC::F28, PPC::F29, PPC::F30, PPC::F31,
-
- PPC::VF0, PPC::VF1, PPC::VF2, PPC::VF3,
- PPC::VF4, PPC::VF5, PPC::VF6, PPC::VF7,
- PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11,
- PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15,
- PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19,
- PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23,
- PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27,
- PPC::VF28, PPC::VF29, PPC::VF30, PPC::VF31
-};
-static const MCPhysReg VSSRegs[64] = {
- PPC::F0, PPC::F1, PPC::F2, PPC::F3,
- PPC::F4, PPC::F5, PPC::F6, PPC::F7,
- PPC::F8, PPC::F9, PPC::F10, PPC::F11,
- PPC::F12, PPC::F13, PPC::F14, PPC::F15,
- PPC::F16, PPC::F17, PPC::F18, PPC::F19,
- PPC::F20, PPC::F21, PPC::F22, PPC::F23,
- PPC::F24, PPC::F25, PPC::F26, PPC::F27,
- PPC::F28, PPC::F29, PPC::F30, PPC::F31,
-
- PPC::VF0, PPC::VF1, PPC::VF2, PPC::VF3,
- PPC::VF4, PPC::VF5, PPC::VF6, PPC::VF7,
- PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11,
- PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15,
- PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19,
- PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23,
- PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27,
- PPC::VF28, PPC::VF29, PPC::VF30, PPC::VF31
-};
-static unsigned QFRegs[32] = {
- PPC::QF0, PPC::QF1, PPC::QF2, PPC::QF3,
- PPC::QF4, PPC::QF5, PPC::QF6, PPC::QF7,
- PPC::QF8, PPC::QF9, PPC::QF10, PPC::QF11,
- PPC::QF12, PPC::QF13, PPC::QF14, PPC::QF15,
- PPC::QF16, PPC::QF17, PPC::QF18, PPC::QF19,
- PPC::QF20, PPC::QF21, PPC::QF22, PPC::QF23,
- PPC::QF24, PPC::QF25, PPC::QF26, PPC::QF27,
- PPC::QF28, PPC::QF29, PPC::QF30, PPC::QF31
-};
-static const MCPhysReg CRBITRegs[32] = {
- PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN,
- PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN,
- PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
- PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
- PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
- PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN,
- PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN,
- PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN
-};
-static const MCPhysReg CRRegs[8] = {
- PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3,
- PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7
-};
+DEFINE_PPC_REGCLASSES;
// Evaluate an expression containing condition register
// or condition register field symbols. Returns positive
Modified: llvm/trunk/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp?rev=350156&r1=350155&r2=350156&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp Sat Dec 29 08:13:11 2018
@@ -17,6 +17,8 @@
using namespace llvm;
+DEFINE_PPC_REGCLASSES;
+
#define DEBUG_TYPE "ppc-disassembler"
typedef MCDisassembler::DecodeStatus DecodeStatus;
@@ -62,184 +64,9 @@ extern "C" void LLVMInitializePowerPCDis
// FIXME: These can be generated by TableGen from the existing register
// encoding values!
-static const unsigned CRRegs[] = {
- PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3,
- PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7
-};
-
-static const unsigned CRBITRegs[] = {
- PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN,
- PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN,
- PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
- PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
- PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
- PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN,
- PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN,
- PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN
-};
-
-static const unsigned FRegs[] = {
- PPC::F0, PPC::F1, PPC::F2, PPC::F3,
- PPC::F4, PPC::F5, PPC::F6, PPC::F7,
- PPC::F8, PPC::F9, PPC::F10, PPC::F11,
- PPC::F12, PPC::F13, PPC::F14, PPC::F15,
- PPC::F16, PPC::F17, PPC::F18, PPC::F19,
- PPC::F20, PPC::F21, PPC::F22, PPC::F23,
- PPC::F24, PPC::F25, PPC::F26, PPC::F27,
- PPC::F28, PPC::F29, PPC::F30, PPC::F31
-};
-
-static const unsigned VFRegs[] = {
- PPC::VF0, PPC::VF1, PPC::VF2, PPC::VF3,
- PPC::VF4, PPC::VF5, PPC::VF6, PPC::VF7,
- PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11,
- PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15,
- PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19,
- PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23,
- PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27,
- PPC::VF28, PPC::VF29, PPC::VF30, PPC::VF31
-};
-
-static const unsigned VRegs[] = {
- PPC::V0, PPC::V1, PPC::V2, PPC::V3,
- PPC::V4, PPC::V5, PPC::V6, PPC::V7,
- PPC::V8, PPC::V9, PPC::V10, PPC::V11,
- PPC::V12, PPC::V13, PPC::V14, PPC::V15,
- PPC::V16, PPC::V17, PPC::V18, PPC::V19,
- PPC::V20, PPC::V21, PPC::V22, PPC::V23,
- PPC::V24, PPC::V25, PPC::V26, PPC::V27,
- PPC::V28, PPC::V29, PPC::V30, PPC::V31
-};
-
-static const unsigned VSRegs[] = {
- PPC::VSL0, PPC::VSL1, PPC::VSL2, PPC::VSL3,
- PPC::VSL4, PPC::VSL5, PPC::VSL6, PPC::VSL7,
- PPC::VSL8, PPC::VSL9, PPC::VSL10, PPC::VSL11,
- PPC::VSL12, PPC::VSL13, PPC::VSL14, PPC::VSL15,
- PPC::VSL16, PPC::VSL17, PPC::VSL18, PPC::VSL19,
- PPC::VSL20, PPC::VSL21, PPC::VSL22, PPC::VSL23,
- PPC::VSL24, PPC::VSL25, PPC::VSL26, PPC::VSL27,
- PPC::VSL28, PPC::VSL29, PPC::VSL30, PPC::VSL31,
-
- PPC::V0, PPC::V1, PPC::V2, PPC::V3,
- PPC::V4, PPC::V5, PPC::V6, PPC::V7,
- PPC::V8, PPC::V9, PPC::V10, PPC::V11,
- PPC::V12, PPC::V13, PPC::V14, PPC::V15,
- PPC::V16, PPC::V17, PPC::V18, PPC::V19,
- PPC::V20, PPC::V21, PPC::V22, PPC::V23,
- PPC::V24, PPC::V25, PPC::V26, PPC::V27,
- PPC::V28, PPC::V29, PPC::V30, PPC::V31
-};
-
-static const unsigned VSFRegs[] = {
- PPC::F0, PPC::F1, PPC::F2, PPC::F3,
- PPC::F4, PPC::F5, PPC::F6, PPC::F7,
- PPC::F8, PPC::F9, PPC::F10, PPC::F11,
- PPC::F12, PPC::F13, PPC::F14, PPC::F15,
- PPC::F16, PPC::F17, PPC::F18, PPC::F19,
- PPC::F20, PPC::F21, PPC::F22, PPC::F23,
- PPC::F24, PPC::F25, PPC::F26, PPC::F27,
- PPC::F28, PPC::F29, PPC::F30, PPC::F31,
-
- PPC::VF0, PPC::VF1, PPC::VF2, PPC::VF3,
- PPC::VF4, PPC::VF5, PPC::VF6, PPC::VF7,
- PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11,
- PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15,
- PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19,
- PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23,
- PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27,
- PPC::VF28, PPC::VF29, PPC::VF30, PPC::VF31
-};
-
-static const unsigned VSSRegs[] = {
- PPC::F0, PPC::F1, PPC::F2, PPC::F3,
- PPC::F4, PPC::F5, PPC::F6, PPC::F7,
- PPC::F8, PPC::F9, PPC::F10, PPC::F11,
- PPC::F12, PPC::F13, PPC::F14, PPC::F15,
- PPC::F16, PPC::F17, PPC::F18, PPC::F19,
- PPC::F20, PPC::F21, PPC::F22, PPC::F23,
- PPC::F24, PPC::F25, PPC::F26, PPC::F27,
- PPC::F28, PPC::F29, PPC::F30, PPC::F31,
-
- PPC::VF0, PPC::VF1, PPC::VF2, PPC::VF3,
- PPC::VF4, PPC::VF5, PPC::VF6, PPC::VF7,
- PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11,
- PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15,
- PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19,
- PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23,
- PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27,
- PPC::VF28, PPC::VF29, PPC::VF30, PPC::VF31
-};
-
-static const unsigned GPRegs[] = {
- PPC::R0, PPC::R1, PPC::R2, PPC::R3,
- PPC::R4, PPC::R5, PPC::R6, PPC::R7,
- PPC::R8, PPC::R9, PPC::R10, PPC::R11,
- PPC::R12, PPC::R13, PPC::R14, PPC::R15,
- PPC::R16, PPC::R17, PPC::R18, PPC::R19,
- PPC::R20, PPC::R21, PPC::R22, PPC::R23,
- PPC::R24, PPC::R25, PPC::R26, PPC::R27,
- PPC::R28, PPC::R29, PPC::R30, PPC::R31
-};
-
-static const unsigned GP0Regs[] = {
- PPC::ZERO, PPC::R1, PPC::R2, PPC::R3,
- PPC::R4, PPC::R5, PPC::R6, PPC::R7,
- PPC::R8, PPC::R9, PPC::R10, PPC::R11,
- PPC::R12, PPC::R13, PPC::R14, PPC::R15,
- PPC::R16, PPC::R17, PPC::R18, PPC::R19,
- PPC::R20, PPC::R21, PPC::R22, PPC::R23,
- PPC::R24, PPC::R25, PPC::R26, PPC::R27,
- PPC::R28, PPC::R29, PPC::R30, PPC::R31
-};
-
-static const unsigned G8Regs[] = {
- PPC::X0, PPC::X1, PPC::X2, PPC::X3,
- PPC::X4, PPC::X5, PPC::X6, PPC::X7,
- PPC::X8, PPC::X9, PPC::X10, PPC::X11,
- PPC::X12, PPC::X13, PPC::X14, PPC::X15,
- PPC::X16, PPC::X17, PPC::X18, PPC::X19,
- PPC::X20, PPC::X21, PPC::X22, PPC::X23,
- PPC::X24, PPC::X25, PPC::X26, PPC::X27,
- PPC::X28, PPC::X29, PPC::X30, PPC::X31
-};
-
-static const unsigned G80Regs[] = {
- PPC::ZERO8, PPC::X1, PPC::X2, PPC::X3,
- PPC::X4, PPC::X5, PPC::X6, PPC::X7,
- PPC::X8, PPC::X9, PPC::X10, PPC::X11,
- PPC::X12, PPC::X13, PPC::X14, PPC::X15,
- PPC::X16, PPC::X17, PPC::X18, PPC::X19,
- PPC::X20, PPC::X21, PPC::X22, PPC::X23,
- PPC::X24, PPC::X25, PPC::X26, PPC::X27,
- PPC::X28, PPC::X29, PPC::X30, PPC::X31
-};
-
-static const unsigned QFRegs[] = {
- PPC::QF0, PPC::QF1, PPC::QF2, PPC::QF3,
- PPC::QF4, PPC::QF5, PPC::QF6, PPC::QF7,
- PPC::QF8, PPC::QF9, PPC::QF10, PPC::QF11,
- PPC::QF12, PPC::QF13, PPC::QF14, PPC::QF15,
- PPC::QF16, PPC::QF17, PPC::QF18, PPC::QF19,
- PPC::QF20, PPC::QF21, PPC::QF22, PPC::QF23,
- PPC::QF24, PPC::QF25, PPC::QF26, PPC::QF27,
- PPC::QF28, PPC::QF29, PPC::QF30, PPC::QF31
-};
-
-static const unsigned SPERegs[] = {
- PPC::S0, PPC::S1, PPC::S2, PPC::S3,
- PPC::S4, PPC::S5, PPC::S6, PPC::S7,
- PPC::S8, PPC::S9, PPC::S10, PPC::S11,
- PPC::S12, PPC::S13, PPC::S14, PPC::S15,
- PPC::S16, PPC::S17, PPC::S18, PPC::S19,
- PPC::S20, PPC::S21, PPC::S22, PPC::S23,
- PPC::S24, PPC::S25, PPC::S26, PPC::S27,
- PPC::S28, PPC::S29, PPC::S30, PPC::S31
-};
-
template <std::size_t N>
static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo,
- const unsigned (&Regs)[N]) {
+ const MCPhysReg (&Regs)[N]) {
assert(RegNo < N && "Invalid register number");
Inst.addOperand(MCOperand::createReg(Regs[RegNo]));
return MCDisassembler::Success;
@@ -308,25 +135,25 @@ static DecodeStatus DecodeVSSRCRegisterC
static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address,
const void *Decoder) {
- return decodeRegisterClass(Inst, RegNo, GPRegs);
+ return decodeRegisterClass(Inst, RegNo, RRegs);
}
static DecodeStatus DecodeGPRC_NOR0RegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address,
const void *Decoder) {
- return decodeRegisterClass(Inst, RegNo, GP0Regs);
+ return decodeRegisterClass(Inst, RegNo, RRegsNoR0);
}
static DecodeStatus DecodeG8RCRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address,
const void *Decoder) {
- return decodeRegisterClass(Inst, RegNo, G8Regs);
+ return decodeRegisterClass(Inst, RegNo, XRegs);
}
static DecodeStatus DecodeG8RC_NOX0RegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address,
const void *Decoder) {
- return decodeRegisterClass(Inst, RegNo, G80Regs);
+ return decodeRegisterClass(Inst, RegNo, XRegsNoX0);
}
#define DecodePointerLikeRegClass0 DecodeGPRCRegisterClass
@@ -341,7 +168,7 @@ static DecodeStatus DecodeQFRCRegisterCl
static DecodeStatus DecodeSPE4RCRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address,
const void *Decoder) {
- return decodeRegisterClass(Inst, RegNo, GPRegs);
+ return decodeRegisterClass(Inst, RegNo, RRegs);
}
static DecodeStatus DecodeSPERCRegisterClass(MCInst &Inst, uint64_t RegNo,
@@ -388,19 +215,19 @@ static DecodeStatus decodeMemRIOperands(
case PPC::LFSU:
case PPC::LFDU:
// Add the tied output operand.
- Inst.addOperand(MCOperand::createReg(GP0Regs[Base]));
+ Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
break;
case PPC::STBU:
case PPC::STHU:
case PPC::STWU:
case PPC::STFSU:
case PPC::STFDU:
- Inst.insert(Inst.begin(), MCOperand::createReg(GP0Regs[Base]));
+ Inst.insert(Inst.begin(), MCOperand::createReg(RRegsNoR0[Base]));
break;
}
Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp)));
- Inst.addOperand(MCOperand::createReg(GP0Regs[Base]));
+ Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
return MCDisassembler::Success;
}
@@ -416,12 +243,12 @@ static DecodeStatus decodeMemRIXOperands
if (Inst.getOpcode() == PPC::LDU)
// Add the tied output operand.
- Inst.addOperand(MCOperand::createReg(GP0Regs[Base]));
+ Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
else if (Inst.getOpcode() == PPC::STDU)
- Inst.insert(Inst.begin(), MCOperand::createReg(GP0Regs[Base]));
+ Inst.insert(Inst.begin(), MCOperand::createReg(RRegsNoR0[Base]));
Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp << 2)));
- Inst.addOperand(MCOperand::createReg(GP0Regs[Base]));
+ Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
return MCDisassembler::Success;
}
@@ -436,7 +263,7 @@ static DecodeStatus decodeMemRIX16Operan
assert(Base < 32 && "Invalid base register");
Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp << 4)));
- Inst.addOperand(MCOperand::createReg(GP0Regs[Base]));
+ Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
return MCDisassembler::Success;
}
@@ -451,7 +278,7 @@ static DecodeStatus decodeSPE8Operands(M
assert(Base < 32 && "Invalid base register");
Inst.addOperand(MCOperand::createImm(Disp << 3));
- Inst.addOperand(MCOperand::createReg(GP0Regs[Base]));
+ Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
return MCDisassembler::Success;
}
@@ -466,7 +293,7 @@ static DecodeStatus decodeSPE4Operands(M
assert(Base < 32 && "Invalid base register");
Inst.addOperand(MCOperand::createImm(Disp << 2));
- Inst.addOperand(MCOperand::createReg(GP0Regs[Base]));
+ Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
return MCDisassembler::Success;
}
@@ -481,7 +308,7 @@ static DecodeStatus decodeSPE2Operands(M
assert(Base < 32 && "Invalid base register");
Inst.addOperand(MCOperand::createImm(Disp << 1));
- Inst.addOperand(MCOperand::createReg(GP0Regs[Base]));
+ Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
return MCDisassembler::Success;
}
Modified: llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h?rev=350156&r1=350155&r2=350156&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h (original)
+++ llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h Sat Dec 29 08:13:11 2018
@@ -17,6 +17,7 @@
// GCC #defines PPC on Linux but we use it as our namespace name
#undef PPC
+#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/Support/MathExtras.h"
#include <cstdint>
#include <memory>
@@ -104,4 +105,63 @@ static inline bool isRunOfOnes(unsigned
#define GET_SUBTARGETINFO_ENUM
#include "PPCGenSubtargetInfo.inc"
+#define PPC_REGS0_31(X) \
+ { \
+ X##0, X##1, X##2, X##3, X##4, X##5, X##6, X##7, X##8, X##9, X##10, X##11, \
+ X##12, X##13, X##14, X##15, X##16, X##17, X##18, X##19, X##20, X##21, \
+ X##22, X##23, X##24, X##25, X##26, X##27, X##28, X##29, X##30, X##31 \
+ }
+
+#define PPC_REGS_NO0_31(Z, X) \
+ { \
+ Z, X##1, X##2, X##3, X##4, X##5, X##6, X##7, X##8, X##9, X##10, X##11, \
+ X##12, X##13, X##14, X##15, X##16, X##17, X##18, X##19, X##20, X##21, \
+ X##22, X##23, X##24, X##25, X##26, X##27, X##28, X##29, X##30, X##31 \
+ }
+
+#define PPC_REGS_LO_HI(LO, HI) \
+ { \
+ LO##0, LO##1, LO##2, LO##3, LO##4, LO##5, LO##6, LO##7, LO##8, LO##9, \
+ LO##10, LO##11, LO##12, LO##13, LO##14, LO##15, LO##16, LO##17, \
+ LO##18, LO##19, LO##20, LO##21, LO##22, LO##23, LO##24, LO##25, \
+ LO##26, LO##27, LO##28, LO##29, LO##30, LO##31, HI##0, HI##1, HI##2, \
+ HI##3, HI##4, HI##5, HI##6, HI##7, HI##8, HI##9, HI##10, HI##11, \
+ HI##12, HI##13, HI##14, HI##15, HI##16, HI##17, HI##18, HI##19, \
+ HI##20, HI##21, HI##22, HI##23, HI##24, HI##25, HI##26, HI##27, \
+ HI##28, HI##29, HI##30, HI##31 \
+ }
+
+using llvm::MCPhysReg;
+
+#define DEFINE_PPC_REGCLASSES \
+ static const MCPhysReg RRegs[32] = PPC_REGS0_31(PPC::R); \
+ static const MCPhysReg XRegs[32] = PPC_REGS0_31(PPC::X); \
+ static const MCPhysReg FRegs[32] = PPC_REGS0_31(PPC::F); \
+ static const MCPhysReg SPERegs[32] = PPC_REGS0_31(PPC::S); \
+ static const MCPhysReg VFRegs[32] = PPC_REGS0_31(PPC::VF); \
+ static const MCPhysReg VRegs[32] = PPC_REGS0_31(PPC::V); \
+ static const MCPhysReg QFRegs[32] = PPC_REGS0_31(PPC::QF); \
+ static const MCPhysReg RRegsNoR0[32] = \
+ PPC_REGS_NO0_31(PPC::ZERO, PPC::R); \
+ static const MCPhysReg XRegsNoX0[32] = \
+ PPC_REGS_NO0_31(PPC::ZERO8, PPC::X); \
+ static const MCPhysReg VSRegs[64] = \
+ PPC_REGS_LO_HI(PPC::VSL, PPC::V); \
+ static const MCPhysReg VSFRegs[64] = \
+ PPC_REGS_LO_HI(PPC::F, PPC::VF); \
+ static const MCPhysReg VSSRegs[64] = \
+ PPC_REGS_LO_HI(PPC::F, PPC::VF); \
+ static const MCPhysReg CRBITRegs[32] = { \
+ PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN, \
+ PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN, \
+ PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, \
+ PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, \
+ PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, \
+ PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN, \
+ PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN, \
+ PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN}; \
+ static const MCPhysReg CRRegs[8] = { \
+ PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, \
+ PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7}
+
#endif // LLVM_LIB_TARGET_POWERPC_MCTARGETDESC_PPCMCTARGETDESC_H
More information about the llvm-commits
mailing list