[PATCH] D56082: [X86][SLP] Enable SLP vectorization for 128-bit horizontal X86 instructions (add, sub)

[Anton Afanasyev via Phabricator via llvm-commits]

anton-afanasyev marked 2 inline comments as done.
anton-afanasyev added inline comments.


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Comment at: lib/Target/X86/X86TargetTransformInfo.cpp:150-154
+// MMX 64-bit registers and horizontal 128-bit operations.
+// This also allows vectorizer to use partial vector operations.
+unsigned X86TTIImpl::getMinVectorRegisterBitWidth() const {
+  return 64;
+}
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lebedev.ri wrote:
> I lack context, but will this also handle e.g. `_mm_hadd_epi16()` ?
Yes, phaddw is also handled.


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Comment at: test/Transforms/SLPVectorizer/X86/vec-reg-64bit.ll:12-37
+; SEMI128-LABEL: @add_pairs_128(
+; SEMI128-NEXT:    [[TMP3:%.*]] = extractelement <4 x float> [[TMP0:%.*]], i32 0
+; SEMI128-NEXT:    [[TMP4:%.*]] = extractelement <4 x float> [[TMP0]], i32 1
+; SEMI128-NEXT:    [[TMP5:%.*]] = extractelement <4 x float> [[TMP0]], i32 2
+; SEMI128-NEXT:    [[TMP6:%.*]] = extractelement <4 x float> [[TMP0]], i32 3
+; SEMI128-NEXT:    [[TMP7:%.*]] = insertelement <2 x float> undef, float [[TMP3]], i32 0
+; SEMI128-NEXT:    [[TMP8:%.*]] = insertelement <2 x float> [[TMP7]], float [[TMP5]], i32 1
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lebedev.ri wrote:
> There are no run lines for these prefixes.
Oops, thanks, forget to remove after prefix renaming.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D56082/new/

https://reviews.llvm.org/D56082