[PATCH] D56082: [X86][SLP] Enable SLP vectorization for 128-bit horizontal X86 instructions (add, sub)

[Alexey Bataev via Phabricator via llvm-commits]

ABataev added a comment.

In D56082#1340948 <https://reviews.llvm.org/D56082#1340948>, @anton-afanasyev wrote:

> In D56082#1340924 <https://reviews.llvm.org/D56082#1340924>, @ABataev wrote:
>
> > General question: why 256bit sie of the vector is set is minimal vector register size if the architecture supports 128 bit vectors? TTI should report 128 as the min regsize, not 256. And we don't need all these new options, functions etc.
>
>
> Hi @ABataev , x86 TTI has already been reporting 128 bit vector (TTI->getMinVectorRegisterBitWidth() returns 128), but we actually need 64-bit vectors (high and low parts of 128-bit registers) to be tried by SLPVectorizer to support horizontal 128-bit adds and subs. Though making TTI->getMinVectorRegisterBitWidth() returning 64 would fix this issue as well, we cannot merge these two notions (minimum vector register and minimum semi vector), since getMinVectorRegisterBitWidth() is used in other places.
>
> Maybe the confusion was caused by naming HADDPS as horizontal 128-bit addings (here http://llvm.org/PR32433), and it should be called as horizontal 64-bit vector pair sum (<2 x float> + <2 x float> -> <2 x float>).


Thenit is better to introduce another function in TTI - something like `getMinVectOpWidth()` and use it in SLP vectorizer at least rather than iadding sometthing like semi vector size.


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D56082/new/

https://reviews.llvm.org/D56082