[llvm] r349822 - [GlobalISel][AArch64] Add G_FCEIL to isPreISelGenericFloatingPointOpcode

[Jessica Paquette via llvm-commits]

Author: paquette
Date: Thu Dec 20 13:14:15 2018
New Revision: 349822

URL: http://llvm.org/viewvc/llvm-project?rev=349822&view=rev
Log:
[GlobalISel][AArch64] Add G_FCEIL to isPreISelGenericFloatingPointOpcode

If you don't do this, then if you hit a G_LOAD in getInstrMapping, you'll end
up with GPRs on the G_FCEIL instead of FPRs. This causes a fallback.

Add it to the switch, and add a test verifying that this happens.

Added:
    llvm/trunk/test/CodeGen/AArch64/GlobalISel/regbank-ceil.ll
Modified:
    llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp

Modified: llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp?rev=349822&r1=349821&r2=349822&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp Thu Dec 20 13:14:15 2018
@@ -389,6 +389,7 @@ static bool isPreISelGenericFloatingPoin
   case TargetOpcode::G_FCONSTANT:
   case TargetOpcode::G_FPEXT:
   case TargetOpcode::G_FPTRUNC:
+  case TargetOpcode::G_FCEIL:
     return true;
   }
   return false;

Added: llvm/trunk/test/CodeGen/AArch64/GlobalISel/regbank-ceil.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/regbank-ceil.ll?rev=349822&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/regbank-ceil.ll (added)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/regbank-ceil.ll Thu Dec 20 13:14:15 2018
@@ -0,0 +1,16 @@
+; RUN: llc -O=0 -verify-machineinstrs -mtriple aarch64--- \
+; RUN: -stop-before=instruction-select -global-isel %s -o - | FileCheck %s
+
+; Make sure that we choose a FPR for the G_FCEIL and G_LOAD instead of a GPR.
+
+declare float @llvm.ceil.f32(float)
+
+; CHECK-LABEL: name:            foo
+define float @foo(float) {
+  store float %0, float* undef, align 4
+  ; CHECK: %2:fpr(s32) = G_LOAD %1(p0)
+  ; CHECK-NEXT: %3:fpr(s32) = G_FCEIL %2
+  %2 = load float, float* undef, align 4
+  %3 = call float @llvm.ceil.f32(float %2)
+  ret float %3
+}