[PATCH] D55935: [X86][SSE] Canonicalize OR(AND(X, C), AND(Y, ~C)) -> OR(AND(X, C), ANDNP(C, Y))

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon created this revision.
RKSimon added reviewers: spatel, craig.topper, lebedev.ri.

For constant bit select patterns, replace one AND with a ANDNP, allowing us to reuse the constant mask. This prevents some load-folding but removes a constant pool vector entry, which I think is the right trade off.

I haven't worked out what is going on in the combine-fcopysign.ll regressions yet - I thinks its a KnownBits/SimplifyDemandedBits issue but need to investigate further.


Repository:
  rL LLVM

https://reviews.llvm.org/D55935

Files:
  lib/Target/X86/X86ISelLowering.cpp
  test/CodeGen/X86/bitreverse.ll
  test/CodeGen/X86/combine-fcopysign.ll
  test/CodeGen/X86/combine-udiv.ll
  test/CodeGen/X86/sse-fcopysign.ll
  test/CodeGen/X86/vec-copysign-avx512.ll
  test/CodeGen/X86/vec-copysign.ll
  test/CodeGen/X86/vector-bitreverse.ll
  test/CodeGen/X86/vector-fshl-128.ll
  test/CodeGen/X86/vector-fshl-256.ll
  test/CodeGen/X86/vector-fshl-512.ll
  test/CodeGen/X86/vector-fshl-rot-128.ll
  test/CodeGen/X86/vector-fshl-rot-256.ll
  test/CodeGen/X86/vector-fshl-rot-512.ll
  test/CodeGen/X86/vector-fshr-128.ll
  test/CodeGen/X86/vector-fshr-256.ll
  test/CodeGen/X86/vector-fshr-512.ll
  test/CodeGen/X86/vector-fshr-rot-128.ll
  test/CodeGen/X86/vector-fshr-rot-256.ll
  test/CodeGen/X86/vector-fshr-rot-512.ll
  test/CodeGen/X86/vector-rotate-128.ll
  test/CodeGen/X86/vector-rotate-256.ll
  test/CodeGen/X86/vector-rotate-512.ll

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