[llvm] r349723 - Fix build errors introduced by r349712 on aarch64 bots.

[Amara Emerson via llvm-commits]

Author: aemerson
Date: Wed Dec 19 19:27:42 2018
New Revision: 349723

URL: http://llvm.org/viewvc/llvm-project?rev=349723&view=rev
Log:
Fix build errors introduced by r349712 on aarch64 bots.

Modified:
    llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp
    llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-scalar-merge.mir

Modified: llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp?rev=349723&r1=349722&r2=349723&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp Wed Dec 19 19:27:42 2018
@@ -1625,10 +1625,9 @@ bool AArch64InstructionSelector::selectM
                                 .addImm(0)
                                 .addUse(I.getOperand(2).getReg())
                                 .addImm(AArch64::sub_32);
-  unsigned BFMDef = MRI.createVirtualRegister(DstRC);
   MachineInstr &BFM =
       *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(AArch64::BFMXri))
-           .addDef(BFMDef)
+           .addDef(I.getOperand(0).getReg())
            .addUse(SubToRegDef)
            .addUse(SubToRegDef2)
            .addImm(32)

Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-scalar-merge.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-scalar-merge.mir?rev=349723&r1=349722&r2=349723&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-scalar-merge.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-scalar-merge.mir Wed Dec 19 19:27:42 2018
@@ -21,12 +21,12 @@ body:             |
     liveins: $w0, $w1
 
     ; CHECK-LABEL: name: gmerge_s64_s32
-    ; CHECK: [[COPY:%[0-9]+]]:gpr32all(s32) = COPY $w0
-    ; CHECK: [[COPY1:%[0-9]+]]:gpr32all(s32) = COPY $w1
-    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY]](s32), %subreg.sub_32
-    ; CHECK: [[SUBREG_TO_REG1:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY1]](s32), %subreg.sub_32
+    ; CHECK: [[COPY:%[0-9]+]]:gpr32all = COPY $w0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY $w1
+    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY]], %subreg.sub_32
+    ; CHECK: [[SUBREG_TO_REG1:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.sub_32
     ; CHECK: [[BFMXri:%[0-9]+]]:gpr64 = BFMXri [[SUBREG_TO_REG]], [[SUBREG_TO_REG1]], 32, 31
-    ; CHECK: $x0 = COPY %2:gpr(s64)
+    ; CHECK: $x0 = COPY [[BFMXri]]
     %0(s32) = COPY $w0
     %1(s32) = COPY $w1
     %2(s64) = G_MERGE_VALUES %0(s32), %1(s32)