[PATCH] D55754: [PowerPC] Implement the ”isSelectSupported()“ target hook

[Zhang Kang via Phabricator via llvm-commits]

ZhangKang marked 2 inline comments as done.
ZhangKang added inline comments.


================
Comment at: llvm/test/CodeGen/PowerPC/select-i1-vs-i1.ll:933
-; CHECK: bc 12, [[REG1]], .LBB[[BB1:[0-9_]+]]
-; CHECK: vmr 3, 2
-; CHECK: .LBB[[BB1]]
----------------
steven.zhang wrote:
> Does this mean that, your fix will remove the "vmr 3, 2" ?
Yes, it will remove `vmr 3, 2`.
In fact, before the fix, the dag will generate the following nodes when making the selection.
```
315 SelectionDAG has 22 nodes:
 316   t0: ch = EntryToken
 317           t2: f32,ch = CopyFromReg t0, Register:f32 %0
 318           t4: f32,ch = CopyFromReg t0, Register:f32 %1
 319         t15: i1 = setcc t2, t4, setoeq:ch
 320           t6: f32,ch = CopyFromReg t0, Register:f32 %2
 321           t8: f32,ch = CopyFromReg t0, Register:f32 %3
 322         t14: i1 = setcc t6, t8, setoeq:ch
 323       t17: i1 = setcc t15, t14, seteq:ch
 324       t10: v4f32,ch = CopyFromReg t0, Register:v4f32 %4
 325       t12: v4f32,ch = CopyFromReg t0, Register:v4f32 %5
 326     t18: v4f32 = select t17, t10, t12
 327   t20: ch,glue = CopyToReg t0, Register:v4f32 $v2, t18
 328   t21: ch = PPCISD::RET_FLAG t20, Register:v4f32 $v2, t20:1
```
the corresponding assembly generated is
```
# %bb.0:                                # %entry
	fcmpu 0, 3, 4
	fcmpu 1, 1, 2
	crxor 20, 6, 2
	bc 12, 20, .LBB0_2
# %bb.1:                                # %entry
	vmr	3, 2
.LBB0_2:                                # %entry
	vmr	2, 3
	blr
```

after the fix, the dag will generate the following nodes when making the selection.
```
343 SelectionDAG has 17 nodes:
 344   t0: ch = EntryToken
 345         t2: f32,ch = CopyFromReg t0, Register:f32 %1
 346         t4: f32,ch = CopyFromReg t0, Register:f32 %2
 347       t15: i1 = setcc t2, t4, setoeq:ch
 348         t6: f32,ch = CopyFromReg t0, Register:f32 %3
 349         t8: f32,ch = CopyFromReg t0, Register:f32 %4
 350       t14: i1 = setcc t6, t8, setoeq:ch
 351     t22: ch = br_cc t0, seteq:ch, t15, t14, BasicBlock:ch<select.end 0x1001bacf748>
 352   t21: ch = br t22, BasicBlock:ch<select.false 0x1001bacf680>
```
the corresponding assembly generated is
```
# %bb.0:                                # %entry
	fcmpu 0, 3, 4
	fcmpu 1, 1, 2
	creqv 20, 6, 2
	bclr 12, 20, 0
# %bb.1:                                # %select.false
	vmr	2, 3
	blr
```


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  https://reviews.llvm.org/D55754/new/

https://reviews.llvm.org/D55754