[PATCH] D55810: [Power9] Enable the Out-of-Order scheduling model for P9 hw

[Qing Shan Zhang via Phabricator via llvm-commits]

steven.zhang created this revision.
steven.zhang added reviewers: nemanjai, jsji, kbarton, hfinkel, stefanp.
Herald added subscribers: hiraditya, qcolombet.

When switched to the MI scheduler for P9 <https://reviews.llvm.org/P9>, the hardware is modeled as out of order. However, inside the MI Scheduler algorithm, we still use the in-order scheduling model as the MicroOpBufferSize isn't set. The MI scheduler take it as the hw cannot buffer the op. So, only when all the available instructions issued, the pending instruction could be scheduled. That is not true for our P9 <https://reviews.llvm.org/P9> hw in fact.

This patch is trying to enable the Out-of-Order scheduling model.  The buffer size 44 is picked from the P9 <https://reviews.llvm.org/P9> hw spec, and the perf test indicate that, its value won't hurt the cpu2017.

With this patch,  there are 3 specs improved over 3% and 1 spec deg over 3%. The detail is as follows:

- x264_r:  +6.95%
- cactuBSSN_r: +6.94%
- lbm_r: +4.11%
- xz_r: -3.85%

And the GEOMEAN for all the C/C++ spec in spec2017 is about 0.18% improved. The root cause of the deg of xz_r has been addressed and it is another issue that exposed by this change.


https://reviews.llvm.org/D55810

Files:
  llvm/lib/Target/PowerPC/PPCScheduleP9.td
  llvm/test/CodeGen/PowerPC/PR33671.ll
  llvm/test/CodeGen/PowerPC/VSX-XForm-Scalars.ll
  llvm/test/CodeGen/PowerPC/build-vector-tests.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-p9-f128.ll
  llvm/test/CodeGen/PowerPC/f128-aggregates.ll
  llvm/test/CodeGen/PowerPC/f128-arith.ll
  llvm/test/CodeGen/PowerPC/f128-conv.ll
  llvm/test/CodeGen/PowerPC/f128-passByValue.ll
  llvm/test/CodeGen/PowerPC/f128-truncateNconv.ll
  llvm/test/CodeGen/PowerPC/mi-scheduling-lhs.ll
  llvm/test/CodeGen/PowerPC/mulld.ll
  llvm/test/CodeGen/PowerPC/ppc64-P9-setb.ll
  llvm/test/CodeGen/PowerPC/pre-inc-disable.ll
  llvm/test/CodeGen/PowerPC/scalar_vector_test_2.ll
  llvm/test/CodeGen/PowerPC/scalar_vector_test_4.ll
  llvm/test/CodeGen/PowerPC/store_fptoi.ll
  llvm/test/CodeGen/PowerPC/stwu-sched.ll
  llvm/test/CodeGen/PowerPC/swaps-le-6.ll
  llvm/test/CodeGen/PowerPC/vec-itofp.ll
  llvm/test/CodeGen/PowerPC/vec_conv_fp32_to_i16_elts.ll
  llvm/test/CodeGen/PowerPC/vec_conv_fp32_to_i64_elts.ll
  llvm/test/CodeGen/PowerPC/vec_conv_fp32_to_i8_elts.ll
  llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i16_elts.ll
  llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i32_elts.ll
  llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i8_elts.ll
  llvm/test/CodeGen/PowerPC/vec_conv_fp_to_i_8byte_elts.ll
  llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp32_elts.ll
  llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp64_elts.ll
  llvm/test/CodeGen/PowerPC/vec_conv_i32_to_fp64_elts.ll
  llvm/test/CodeGen/PowerPC/vec_conv_i64_to_fp32_elts.ll
  llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp32_elts.ll
  llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp64_elts.ll
  llvm/test/CodeGen/PowerPC/vec_conv_i_to_fp_8byte_elts.ll
  llvm/test/CodeGen/PowerPC/vsx-p9.ll
  llvm/test/CodeGen/PowerPC/vsx-spill.ll
  llvm/test/CodeGen/PowerPC/vsx_insert_extract_le.ll