[llvm] r349354 - [MCA] Add support for BeginGroup/EndGroup.

[Andrea Di Biagio via llvm-commits]

Author: adibiagio
Date: Mon Dec 17 06:27:33 2018
New Revision: 349354

URL: http://llvm.org/viewvc/llvm-project?rev=349354&view=rev
Log:
[MCA] Add support for BeginGroup/EndGroup.


Modified:
    llvm/trunk/include/llvm/MCA/Instruction.h
    llvm/trunk/lib/MCA/InstrBuilder.cpp
    llvm/trunk/lib/MCA/Stages/DispatchStage.cpp
    llvm/trunk/test/tools/llvm-mca/SystemZ/stm-lm.s

Modified: llvm/trunk/include/llvm/MCA/Instruction.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MCA/Instruction.h?rev=349354&r1=349353&r2=349354&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MCA/Instruction.h (original)
+++ llvm/trunk/include/llvm/MCA/Instruction.h Mon Dec 17 06:27:33 2018
@@ -334,6 +334,8 @@ struct InstrDesc {
   bool MayLoad;
   bool MayStore;
   bool HasSideEffects;
+  bool BeginGroup;
+  bool EndGroup;
 
   // A zero latency instruction doesn't consume any scheduler resources.
   bool isZeroLatency() const { return !MaxLatency && Resources.empty(); }

Modified: llvm/trunk/lib/MCA/InstrBuilder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MCA/InstrBuilder.cpp?rev=349354&r1=349353&r2=349354&view=diff
==============================================================================
--- llvm/trunk/lib/MCA/InstrBuilder.cpp (original)
+++ llvm/trunk/lib/MCA/InstrBuilder.cpp Mon Dec 17 06:27:33 2018
@@ -536,6 +536,8 @@ InstrBuilder::createInstrDescImpl(const
   ID->MayLoad = MCDesc.mayLoad();
   ID->MayStore = MCDesc.mayStore();
   ID->HasSideEffects = MCDesc.hasUnmodeledSideEffects();
+  ID->BeginGroup = SCDesc.BeginGroup;
+  ID->EndGroup = SCDesc.EndGroup;
 
   initializeUsedResources(*ID, SCDesc, STI, ProcResourceMasks);
   computeMaxLatency(*ID, MCDesc, SCDesc, STI);

Modified: llvm/trunk/lib/MCA/Stages/DispatchStage.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MCA/Stages/DispatchStage.cpp?rev=349354&r1=349353&r2=349354&view=diff
==============================================================================
--- llvm/trunk/lib/MCA/Stages/DispatchStage.cpp (original)
+++ llvm/trunk/lib/MCA/Stages/DispatchStage.cpp Mon Dec 17 06:27:33 2018
@@ -99,6 +99,10 @@ Error DispatchStage::dispatch(InstRef IR
     AvailableEntries -= NumMicroOps;
   }
 
+  // Check if this instructions ends the dispatch group.
+  if (Desc.EndGroup)
+    AvailableEntries = 0;
+
   // Check if this is an optimizable reg-reg move.
   bool IsEliminated = false;
   if (IS.isOptimizableMove()) {
@@ -164,6 +168,10 @@ bool DispatchStage::isAvailable(const In
   unsigned Required = std::min(Desc.NumMicroOps, DispatchWidth);
   if (Required > AvailableEntries)
     return false;
+
+  if (Desc.BeginGroup && AvailableEntries != DispatchWidth)
+    return false;
+
   // The dispatch logic doesn't internally buffer instructions.  It only accepts
   // instructions that can be successfully moved to the next stage during this
   // same cycle.

Modified: llvm/trunk/test/tools/llvm-mca/SystemZ/stm-lm.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/tools/llvm-mca/SystemZ/stm-lm.s?rev=349354&r1=349353&r2=349354&view=diff
==============================================================================
--- llvm/trunk/test/tools/llvm-mca/SystemZ/stm-lm.s (original)
+++ llvm/trunk/test/tools/llvm-mca/SystemZ/stm-lm.s Mon Dec 17 06:27:33 2018
@@ -6,7 +6,7 @@ lmg	%r6, %r15, 48(%r15)
 
 # CHECK:      Iterations:        100
 # CHECK-NEXT: Instructions:      200
-# CHECK-NEXT: Total Cycles:      1003
+# CHECK-NEXT: Total Cycles:      1004
 # CHECK-NEXT: Total uOps:        600
 
 # CHECK:      Dispatch Width:    6
@@ -51,15 +51,15 @@ lmg	%r6, %r15, 48(%r15)
 # CHECK-NEXT:  -      -      -      -     0.10   4.90    -      -      -      -      -      -      -     lmg	%r6, %r15, 48(%r15)
 
 # CHECK:      Timeline view:
-# CHECK-NEXT:                     0123456789          012
+# CHECK-NEXT:                     0123456789          0123
 # CHECK-NEXT: Index     0123456789          0123456789
 
-# CHECK:      [0,0]     DeER .    .    .    .    .    . .   stmg	%r6, %r15, 48(%r15)
-# CHECK-NEXT: [0,1]     DeeeeeeeeeeER  .    .    .    . .   lmg	%r6, %r15, 48(%r15)
-# CHECK-NEXT: [1,0]     .D=========eER .    .    .    . .   stmg	%r6, %r15, 48(%r15)
-# CHECK-NEXT: [1,1]     .D=========eeeeeeeeeeER  .    . .   lmg	%r6, %r15, 48(%r15)
-# CHECK-NEXT: [2,0]     . D==================eER .    . .   stmg	%r6, %r15, 48(%r15)
-# CHECK-NEXT: [2,1]     . D==================eeeeeeeeeeER   lmg	%r6, %r15, 48(%r15)
+# CHECK:      [0,0]     DeER .    .    .    .    .    .  .   stmg	%r6, %r15, 48(%r15)
+# CHECK-NEXT: [0,1]     .DeeeeeeeeeeER .    .    .    .  .   lmg	%r6, %r15, 48(%r15)
+# CHECK-NEXT: [1,0]     . D=========eER.    .    .    .  .   stmg	%r6, %r15, 48(%r15)
+# CHECK-NEXT: [1,1]     .  D========eeeeeeeeeeER .    .  .   lmg	%r6, %r15, 48(%r15)
+# CHECK-NEXT: [2,0]     .   D=================eER.    .  .   stmg	%r6, %r15, 48(%r15)
+# CHECK-NEXT: [2,1]     .    D================eeeeeeeeeeER   lmg	%r6, %r15, 48(%r15)
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
@@ -68,5 +68,5 @@ lmg	%r6, %r15, 48(%r15)
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
-# CHECK-NEXT: 0.     3     10.0   0.3    0.0       stmg	%r6, %r15, 48(%r15)
-# CHECK-NEXT: 1.     3     10.0   0.3    0.0       lmg	%r6, %r15, 48(%r15)
+# CHECK-NEXT: 0.     3     9.7    0.3    0.0       stmg	%r6, %r15, 48(%r15)
+# CHECK-NEXT: 1.     3     9.0    0.3    0.0       lmg	%r6, %r15, 48(%r15)