[llvm] r349346 - [MIPS GlobalISel] Lower G_UADDE and narrowScalar G_ADD
Petar Avramovic via llvm-commits
llvm-commits at lists.llvm.org
Mon Dec 17 04:31:07 PST 2018
Author: petar.avramovic
Date: Mon Dec 17 04:31:07 2018
New Revision: 349346
URL: http://llvm.org/viewvc/llvm-project?rev=349346&view=rev
Log:
[MIPS GlobalISel] Lower G_UADDE and narrowScalar G_ADD
Lower G_UADDE and legalize G_ADD using narrowScalar on MIPS32.
Differential Revision: https://reviews.llvm.org/D54580
Modified:
llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
llvm/trunk/lib/Target/Mips/MipsLegalizerInfo.cpp
llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/add.mir
llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/add.ll
Modified: llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp?rev=349346&r1=349345&r2=349346&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp (original)
+++ llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp Mon Dec 17 04:31:07 2018
@@ -1119,6 +1119,24 @@ LegalizerHelper::lower(MachineInstr &MI,
case TargetOpcode::G_CTTZ:
case TargetOpcode::G_CTPOP:
return lowerBitCount(MI, TypeIdx, Ty);
+ case G_UADDE: {
+ unsigned Res = MI.getOperand(0).getReg();
+ unsigned CarryOut = MI.getOperand(1).getReg();
+ unsigned LHS = MI.getOperand(2).getReg();
+ unsigned RHS = MI.getOperand(3).getReg();
+ unsigned CarryIn = MI.getOperand(4).getReg();
+
+ unsigned TmpRes = MRI.createGenericVirtualRegister(Ty);
+ unsigned ZExtCarryIn = MRI.createGenericVirtualRegister(Ty);
+
+ MIRBuilder.buildAdd(TmpRes, LHS, RHS);
+ MIRBuilder.buildZExt(ZExtCarryIn, CarryIn);
+ MIRBuilder.buildAdd(Res, TmpRes, ZExtCarryIn);
+ MIRBuilder.buildICmp(CmpInst::ICMP_ULT, CarryOut, Res, LHS);
+
+ MI.eraseFromParent();
+ return Legalized;
+ }
}
}
Modified: llvm/trunk/lib/Target/Mips/MipsLegalizerInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsLegalizerInfo.cpp?rev=349346&r1=349345&r2=349346&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsLegalizerInfo.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsLegalizerInfo.cpp Mon Dec 17 04:31:07 2018
@@ -20,14 +20,16 @@ using namespace llvm;
MipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) {
using namespace TargetOpcode;
+ const LLT s1 = LLT::scalar(1);
const LLT s32 = LLT::scalar(32);
- const LLT s64 = LLT::scalar(64);
const LLT p0 = LLT::pointer(0, 32);
getActionDefinitionsBuilder(G_ADD)
.legalFor({s32})
- .minScalar(0, s32)
- .customFor({s64});
+ .clampScalar(0, s32, s32);
+
+ getActionDefinitionsBuilder(G_UADDE)
+ .lowerFor({{s32, s1}});
getActionDefinitionsBuilder({G_LOAD, G_STORE})
.legalForCartesianProduct({p0, s32}, {p0});
@@ -66,33 +68,6 @@ bool MipsLegalizerInfo::legalizeCustom(M
MIRBuilder.setInstr(MI);
switch (MI.getOpcode()) {
- case G_ADD: {
- unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
-
- const LLT sHalf = LLT::scalar(Size / 2);
-
- unsigned RHSLow = MRI.createGenericVirtualRegister(sHalf);
- unsigned RHSHigh = MRI.createGenericVirtualRegister(sHalf);
- unsigned LHSLow = MRI.createGenericVirtualRegister(sHalf);
- unsigned LHSHigh = MRI.createGenericVirtualRegister(sHalf);
- unsigned ResLow = MRI.createGenericVirtualRegister(sHalf);
- unsigned ResHigh = MRI.createGenericVirtualRegister(sHalf);
- unsigned Carry = MRI.createGenericVirtualRegister(sHalf);
- unsigned TmpResHigh = MRI.createGenericVirtualRegister(sHalf);
-
- MIRBuilder.buildUnmerge({RHSLow, RHSHigh}, MI.getOperand(2).getReg());
- MIRBuilder.buildUnmerge({LHSLow, LHSHigh}, MI.getOperand(1).getReg());
-
- MIRBuilder.buildAdd(TmpResHigh, LHSHigh, RHSHigh);
- MIRBuilder.buildAdd(ResLow, LHSLow, RHSLow);
- MIRBuilder.buildICmp(CmpInst::ICMP_ULT, Carry, ResLow, LHSLow);
- MIRBuilder.buildAdd(ResHigh, TmpResHigh, Carry);
-
- MIRBuilder.buildMerge(MI.getOperand(0).getReg(), {ResLow, ResHigh});
-
- MI.eraseFromParent();
- break;
- }
default:
return false;
}
Modified: llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/add.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/add.mir?rev=349346&r1=349345&r2=349346&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/add.mir (original)
+++ llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/add.mir Mon Dec 17 04:31:07 2018
@@ -10,6 +10,7 @@
define void @add_i16_zext() {entry: ret void}
define void @add_i16_aext() {entry: ret void}
define void @add_i64() {entry: ret void}
+ define void @add_i128() {entry: ret void}
...
---
@@ -226,11 +227,19 @@ body: |
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
- ; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY2]], [[COPY]]
- ; MIPS32: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY3]], [[COPY1]]
+ ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY3]], [[COPY1]]
+ ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; MIPS32: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ADD]], [[AND]]
; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD1]](s32), [[COPY3]]
- ; MIPS32: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ADD]], [[ICMP]]
- ; MIPS32: $v0 = COPY [[ADD2]](s32)
+ ; MIPS32: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[COPY2]], [[COPY]]
+ ; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
+ ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C2]]
+ ; MIPS32: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ADD2]], [[AND1]]
+ ; MIPS32: $v0 = COPY [[ADD3]](s32)
; MIPS32: $v1 = COPY [[ADD1]](s32)
; MIPS32: RetRA implicit $v0, implicit $v1
%2:_(s32) = COPY $a0
@@ -246,3 +255,82 @@ body: |
RetRA implicit $v0, implicit $v1
...
+---
+name: add_i128
+alignment: 2
+tracksRegLiveness: true
+fixedStack:
+ - { id: 0, offset: 28, size: 4, alignment: 4, stack-id: 0, isImmutable: true }
+ - { id: 1, offset: 24, size: 4, alignment: 8, stack-id: 0, isImmutable: true }
+ - { id: 2, offset: 20, size: 4, alignment: 4, stack-id: 0, isImmutable: true }
+ - { id: 3, offset: 16, size: 4, alignment: 8, stack-id: 0, isImmutable: true }
+body: |
+ bb.1.entry:
+ liveins: $a0, $a1, $a2, $a3
+
+ ; MIPS32-LABEL: name: add_i128
+ ; MIPS32: liveins: $a0, $a1, $a2, $a3
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
+ ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
+ ; MIPS32: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
+ ; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load 4 from %fixed-stack.0, align 0)
+ ; MIPS32: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
+ ; MIPS32: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p0) :: (load 4 from %fixed-stack.1, align 0)
+ ; MIPS32: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2
+ ; MIPS32: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX2]](p0) :: (load 4 from %fixed-stack.2, align 0)
+ ; MIPS32: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.3
+ ; MIPS32: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX3]](p0) :: (load 4 from %fixed-stack.3, align 0)
+ ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LOAD]], [[COPY]]
+ ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; MIPS32: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ADD]], [[AND]]
+ ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD1]](s32), [[LOAD]]
+ ; MIPS32: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[LOAD1]], [[COPY1]]
+ ; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
+ ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C2]]
+ ; MIPS32: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ADD2]], [[AND1]]
+ ; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD3]](s32), [[LOAD1]]
+ ; MIPS32: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[LOAD2]], [[COPY2]]
+ ; MIPS32: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32)
+ ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; MIPS32: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[ADD4]], [[AND2]]
+ ; MIPS32: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD5]](s32), [[LOAD2]]
+ ; MIPS32: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[LOAD3]], [[COPY3]]
+ ; MIPS32: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; MIPS32: [[COPY7:%[0-9]+]]:_(s32) = COPY [[ICMP2]](s32)
+ ; MIPS32: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C4]]
+ ; MIPS32: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[ADD6]], [[AND3]]
+ ; MIPS32: $v0 = COPY [[ADD1]](s32)
+ ; MIPS32: $v1 = COPY [[ADD3]](s32)
+ ; MIPS32: $a0 = COPY [[ADD5]](s32)
+ ; MIPS32: $a1 = COPY [[ADD7]](s32)
+ ; MIPS32: RetRA implicit $v0, implicit $v1, implicit $a0, implicit $a1
+ %2:_(s32) = COPY $a0
+ %3:_(s32) = COPY $a1
+ %4:_(s32) = COPY $a2
+ %5:_(s32) = COPY $a3
+ %0:_(s128) = G_MERGE_VALUES %2(s32), %3(s32), %4(s32), %5(s32)
+ %10:_(p0) = G_FRAME_INDEX %fixed-stack.3
+ %6:_(s32) = G_LOAD %10(p0) :: (load 4 from %fixed-stack.3, align 0)
+ %11:_(p0) = G_FRAME_INDEX %fixed-stack.2
+ %7:_(s32) = G_LOAD %11(p0) :: (load 4 from %fixed-stack.2, align 0)
+ %12:_(p0) = G_FRAME_INDEX %fixed-stack.1
+ %8:_(s32) = G_LOAD %12(p0) :: (load 4 from %fixed-stack.1, align 0)
+ %13:_(p0) = G_FRAME_INDEX %fixed-stack.0
+ %9:_(s32) = G_LOAD %13(p0) :: (load 4 from %fixed-stack.0, align 0)
+ %1:_(s128) = G_MERGE_VALUES %6(s32), %7(s32), %8(s32), %9(s32)
+ %14:_(s128) = G_ADD %1, %0
+ %15:_(s32), %16:_(s32), %17:_(s32), %18:_(s32) = G_UNMERGE_VALUES %14(s128)
+ $v0 = COPY %15(s32)
+ $v1 = COPY %16(s32)
+ $a0 = COPY %17(s32)
+ $a1 = COPY %18(s32)
+ RetRA implicit $v0, implicit $v1, implicit $a0, implicit $a1
+
+...
Modified: llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/add.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/add.ll?rev=349346&r1=349345&r2=349346&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/add.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/add.ll Mon Dec 17 04:31:07 2018
@@ -90,14 +90,73 @@ entry:
define i64 @add_i64(i64 %a, i64 %b) {
; MIPS32-LABEL: add_i64:
; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: addu $5, $7, $5
+; MIPS32-NEXT: lui $1, 0
+; MIPS32-NEXT: ori $1, $1, 0
; MIPS32-NEXT: addu $4, $6, $4
-; MIPS32-NEXT: sltu $6, $4, $6
-; MIPS32-NEXT: addu $3, $5, $6
-; MIPS32-NEXT: move $2, $4
+; MIPS32-NEXT: lui $2, 0
+; MIPS32-NEXT: ori $2, $2, 1
+; MIPS32-NEXT: and $1, $1, $2
+; MIPS32-NEXT: addu $1, $4, $1
+; MIPS32-NEXT: sltu $2, $1, $6
+; MIPS32-NEXT: addu $4, $7, $5
+; MIPS32-NEXT: lui $5, 0
+; MIPS32-NEXT: ori $5, $5, 1
+; MIPS32-NEXT: and $2, $2, $5
+; MIPS32-NEXT: addu $3, $4, $2
+; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
%add = add i64 %b, %a
ret i64 %add
-}
\ No newline at end of file
+}
+
+define i128 @add_i128(i128 %a, i128 %b) {
+; MIPS32-LABEL: add_i128:
+; MIPS32: # %bb.0: # %entry
+; MIPS32-NEXT: addiu $sp, $sp, -8
+; MIPS32-NEXT: .cfi_def_cfa_offset 8
+; MIPS32-NEXT: addiu $1, $sp, 24
+; MIPS32-NEXT: lw $1, 0($1)
+; MIPS32-NEXT: addiu $2, $sp, 28
+; MIPS32-NEXT: lw $2, 0($2)
+; MIPS32-NEXT: addiu $3, $sp, 32
+; MIPS32-NEXT: lw $3, 0($3)
+; MIPS32-NEXT: addiu $8, $sp, 36
+; MIPS32-NEXT: lw $8, 0($8)
+; MIPS32-NEXT: lui $9, 0
+; MIPS32-NEXT: ori $9, $9, 0
+; MIPS32-NEXT: addu $4, $1, $4
+; MIPS32-NEXT: lui $10, 0
+; MIPS32-NEXT: ori $10, $10, 1
+; MIPS32-NEXT: and $9, $9, $10
+; MIPS32-NEXT: addu $4, $4, $9
+; MIPS32-NEXT: sltu $1, $4, $1
+; MIPS32-NEXT: addu $5, $2, $5
+; MIPS32-NEXT: lui $9, 0
+; MIPS32-NEXT: ori $9, $9, 1
+; MIPS32-NEXT: and $1, $1, $9
+; MIPS32-NEXT: addu $1, $5, $1
+; MIPS32-NEXT: sltu $2, $1, $2
+; MIPS32-NEXT: addu $5, $3, $6
+; MIPS32-NEXT: lui $6, 0
+; MIPS32-NEXT: ori $6, $6, 1
+; MIPS32-NEXT: and $2, $2, $6
+; MIPS32-NEXT: addu $2, $5, $2
+; MIPS32-NEXT: sltu $3, $2, $3
+; MIPS32-NEXT: addu $5, $8, $7
+; MIPS32-NEXT: lui $6, 0
+; MIPS32-NEXT: ori $6, $6, 1
+; MIPS32-NEXT: and $3, $3, $6
+; MIPS32-NEXT: addu $5, $5, $3
+; MIPS32-NEXT: sw $2, 4($sp) # 4-byte Folded Spill
+; MIPS32-NEXT: move $2, $4
+; MIPS32-NEXT: move $3, $1
+; MIPS32-NEXT: lw $4, 4($sp) # 4-byte Folded Reload
+; MIPS32-NEXT: addiu $sp, $sp, 8
+; MIPS32-NEXT: jr $ra
+; MIPS32-NEXT: nop
+entry:
+ %add = add i128 %b, %a
+ ret i128 %add
+}
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