[llvm] r349202 - [Hexagon] Add patterns for shifts of v2i16

[Krzysztof Parzyszek via llvm-commits]

Author: kparzysz
Date: Fri Dec 14 14:33:48 2018
New Revision: 349202

URL: http://llvm.org/viewvc/llvm-project?rev=349202&view=rev
Log:
[Hexagon] Add patterns for shifts of v2i16

This fixes https://llvm.org/PR39983.

Added:
    llvm/trunk/test/CodeGen/Hexagon/isel-vlsr-v2i16.ll
Modified:
    llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td

Modified: llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td?rev=349202&r1=349201&r2=349202&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td Fri Dec 14 14:33:48 2018
@@ -1170,6 +1170,18 @@ def: Pat<(srl V4I16:$b, (v4i16 (HexagonV
 def: Pat<(shl V4I16:$b, (v4i16 (HexagonVSPLAT u4_0ImmPred:$c))),
          (S2_asl_i_vh V4I16:$b, imm:$c)>;
 
+def: Pat<(HexagonVASR V2I16:$Rs, u4_0ImmPred:$S),
+         (LoReg (S2_asr_i_vh (ToAext64 $Rs), imm:$S))>;
+def: Pat<(HexagonVASL V2I16:$Rs, u4_0ImmPred:$S),
+         (LoReg (S2_asl_i_vh (ToAext64 $Rs), imm:$S))>;
+def: Pat<(HexagonVLSR V2I16:$Rs, u4_0ImmPred:$S),
+         (LoReg (S2_lsr_i_vh (ToAext64 $Rs), imm:$S))>;
+def: Pat<(HexagonVASR V2I16:$Rs, I32:$Rt),
+         (LoReg (S2_asr_i_vh (ToAext64 $Rs), I32:$Rt))>;
+def: Pat<(HexagonVASL V2I16:$Rs, I32:$Rt),
+         (LoReg (S2_asl_i_vh (ToAext64 $Rs), I32:$Rt))>;
+def: Pat<(HexagonVLSR V2I16:$Rs, I32:$Rt),
+         (LoReg (S2_lsr_i_vh (ToAext64 $Rs), I32:$Rt))>;
 
 // --(9) Arithmetic/bitwise ----------------------------------------------
 //

Added: llvm/trunk/test/CodeGen/Hexagon/isel-vlsr-v2i16.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/isel-vlsr-v2i16.ll?rev=349202&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/isel-vlsr-v2i16.ll (added)
+++ llvm/trunk/test/CodeGen/Hexagon/isel-vlsr-v2i16.ll Fri Dec 14 14:33:48 2018
@@ -0,0 +1,16 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+
+; This used to crash with "cannot select" error.
+; CHECK: vlsrh(r1:0,#4)
+
+target triple = "hexagon-unknown-linux-gnu"
+
+define <2 x i16> @foo(<2 x i32>* nocapture %v) nounwind {
+  %vec = load <2 x i32>, <2 x i32>* %v, align 8
+  %trunc = trunc <2 x i32> %vec to <2 x i16>
+  %r = lshr <2 x i16> %trunc, <i16 4, i16 4>
+  ret <2 x i16> %r
+}
+
+attributes #0 = { nounwind "target-cpu"="hexagonv60" }
+