[PATCH] D55686: [PowerPC] Fix assert from machine verify pass that unmatched register class about fcmp selection in fast-isel

Zixuan Wu via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Dec 13 18:51:23 PST 2018


wuzish created this revision.
wuzish added reviewers: hfinkel, nemanjai, wschmidt, jsji.
Herald added subscribers: kbarton, hiraditya.

The way to reproduce the issue:

  llc -mtriple powerpc64le-unknown-linux-gnu -fast-isel -O0 < llvm/test/CodeGen/PowerPC/fast-isel-fcmp-nan.ll -verify-machineinstrs
  
  Bad machine code: Illegal virtual register for instruction
  
  function: TestULE
  basic block: %bb.0 entry (0x1000a39b158)
  instruction: %2:crrc = FCMPUD %1:vsfrc, %3:f8rc
  operand 1: %1:vsfrc

Fix assert about missing match between fcmp instruction and register class. We should use vsx related cmp instruction xvcmpudp instead of fcmpu when vsx is opened.

add -verifymachineinstrs option into related test cases to enable the verify pass.

@wschmidt could you please have a look since the last change is related to your part? Thanks.


Repository:
  rL LLVM

https://reviews.llvm.org/D55686

Files:
  llvm/lib/Target/PowerPC/PPCFastISel.cpp
  llvm/test/CodeGen/PowerPC/fast-isel-fcmp-nan.ll
  llvm/test/CodeGen/PowerPC/vsx-self-copy.ll


Index: llvm/test/CodeGen/PowerPC/vsx-self-copy.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/vsx-self-copy.ll
+++ llvm/test/CodeGen/PowerPC/vsx-self-copy.ll
@@ -1,5 +1,5 @@
-; RUN: llc -mcpu=pwr7 -mattr=+vsx < %s | FileCheck %s
-; RUN: llc -mcpu=pwr7 -mattr=+vsx -fast-isel -O0 < %s | FileCheck %s
+; RUN: llc -mcpu=pwr7 -mattr=+vsx < %s -verify-machineinstrs | FileCheck %s
+; RUN: llc -mcpu=pwr7 -mattr=+vsx -fast-isel -O0 < %s -verify-machineinstrs | FileCheck %s
 target datalayout = "E-m:e-i64:64-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
Index: llvm/test/CodeGen/PowerPC/fast-isel-fcmp-nan.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/fast-isel-fcmp-nan.ll
+++ llvm/test/CodeGen/PowerPC/fast-isel-fcmp-nan.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple powerpc64le-unknown-linux-gnu -fast-isel -O0 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple powerpc64le-unknown-linux-gnu -fast-isel -O0 < %s | FileCheck %s
 
 define i1 @TestULT(double %t0) {
 ; CHECK-LABEL: TestULT:
@@ -17,7 +17,7 @@
 
 define i1 @TestULE(double %t0) {
 ; CHECK-LABEL: TestULE:
-; CHECK: fcmpu
+; CHECK: xscmpudp
 ; CHECK-NEXT: ble
 ; CHECK: blr
 entry:
@@ -33,7 +33,7 @@
 
 define i1 @TestUNE(double %t0) {
 ; CHECK-LABEL: TestUNE:
-; CHECK: fcmpu
+; CHECK: xscmpudp
 ; CHECK-NEXT: bne
 ; CHECK: blr
 entry:
@@ -79,7 +79,7 @@
 
 define i1 @TestUGE(double %t0) {
 ; CHECK-LABEL: TestUGE:
-; CHECK: fcmpu
+; CHECK: xscmpudp
 ; CHECK-NEXT: bge
 ; CHECK: blr
 entry:
@@ -95,7 +95,7 @@
 
 define i1 @TestOLT(double %t0) {
 ; CHECK-LABEL: TestOLT:
-; CHECK: fcmpu
+; CHECK: xscmpudp
 ; CHECK-NEXT: blt
 ; CHECK: blr
 entry:
@@ -141,7 +141,7 @@
 
 define i1 @TestOEQ(double %t0) {
 ; CHECK-LABEL: TestOEQ:
-; CHECK: fcmpu
+; CHECK: xscmpudp
 ; CHECK-NEXT: beq
 ; CHECK: blr
 entry:
@@ -157,7 +157,7 @@
 
 define i1 @TestOGT(double %t0) {
 ; CHECK-LABEL: TestOGT:
-; CHECK: fcmpu
+; CHECK: xscmpudp
 ; CHECK-NEXT: bgt
 ; CHECK: blr
 entry:
Index: llvm/lib/Target/PowerPC/PPCFastISel.cpp
===================================================================
--- llvm/lib/Target/PowerPC/PPCFastISel.cpp
+++ llvm/lib/Target/PowerPC/PPCFastISel.cpp
@@ -897,7 +897,7 @@
             break;
         }
       } else
-        CmpOpc = PPC::FCMPUD;
+        CmpOpc = PPCSubTarget->hasVSX() ? PPC::XSCMPUDP : PPC::FCMPUD;
       break;
     case MVT::i1:
     case MVT::i8:


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