[PATCH] D53230: [RISCV] Introduce codegen patterns for RV64M-only instructions

[Alex Bradbury via Phabricator via llvm-commits]

asb planned changes to this revision.
asb added a comment.

Marking as "planned changes". At least the following patterns are problematic:

  def : Pat<(udiv (zexti32 GPR:$rs1), (zexti32 GPR:$rs2)),
            (DIVUW GPR:$rs1, GPR:$rs2)>;
  def : Pat<(urem (zexti32 GPR:$rs1), (zexti32 GPR:$rs2)),
            (REMUW GPR:$rs1, GPR:$rs2)>;

DIVUW and REMUW will sign-extend the result so this pattern is only safe if we know that the upper 32-bits of the result aren't used.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D53230/new/

https://reviews.llvm.org/D53230