[PATCH] D54896: Introduce control flow speculation tracking pass for AArch64.

[Kristof Beyls via Phabricator via llvm-commits]

kristof.beyls updated this revision to Diff 177843.
kristof.beyls added a comment.

This updated diff addresses Oliver's final comment, namely about what to do when the program uses X16, e.g because of use of inline assembly specifically requesting to use X16.
Besides all the options I came up with previously, there is a 4th option: prevent speculation by inserting DSB SYS/ISB instruction pairs. Conceptually this is not unlike using lfence in X86SpeculativeLoadHardening.
I believe the pros/cons of this approach are (compared to the 3 options I listed previously):
Pros:

- A relatively simple implementation.
- Still keeping the advantages of doing speculation hardening very late.
- No silent non-protected code.
- This alternative protection mechanism is expected to only be needed for a very small amount of code.

Cons:

- This likely has higher overhead than if we could still use a data flow mechanism to track when control flow miss-speculation happens.

Overall, this method seems to offer the best trade-off out of all options listed.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D54896/new/

https://reviews.llvm.org/D54896

Files:
  lib/Target/AArch64/AArch64.h
  lib/Target/AArch64/AArch64FastISel.cpp
  lib/Target/AArch64/AArch64ISelLowering.cpp
  lib/Target/AArch64/AArch64InstrInfo.cpp
  lib/Target/AArch64/AArch64InstructionSelector.cpp
  lib/Target/AArch64/AArch64RegisterInfo.cpp
  lib/Target/AArch64/AArch64SpeculationHardening.cpp
  lib/Target/AArch64/AArch64TargetMachine.cpp
  lib/Target/AArch64/CMakeLists.txt
  test/CodeGen/AArch64/O0-pipeline.ll
  test/CodeGen/AArch64/O3-pipeline.ll
  test/CodeGen/AArch64/speculation-hardening-dagisel.ll
  test/CodeGen/AArch64/speculation-hardening.ll
  test/CodeGen/AArch64/speculation-hardening.mir

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