[PATCH] D55572: [AArch64] Add patterns for zext/sext of shift amount.

[Tim Northover via Phabricator via llvm-commits]

t.p.northover added inline comments.


================
Comment at: test/CodeGen/AArch64/shift-mod.ll:21-22
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    neg w8, w0
+; CHECK-NEXT:    asr x0, x1, x8
+; CHECK-NEXT:    ret
----------------
There's no particular reason to use w8 here so this test is pretty fragile. In general I think we should never be hard-coding registers that aren't at an ABI boundary (and so that update_llc_test_checks.py is usually more trouble than it's worth).


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D55572/new/

https://reviews.llvm.org/D55572