[PATCH] D55460: APFloat: allow 64-bit of payload

[John McCall via Phabricator via llvm-commits]

rjmccall added a comment.

This truncates the payload to fit into the significand field.  Presumably that includes setting the top bit of the significand to make this a NaN and not an infinity.  Does it also always form a qNaN, or can you create an sNaN this way?


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D55460/new/

https://reviews.llvm.org/D55460