[PATCH] D55402: [AMDGPU] Simplify negated condition

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp:166
+    std::swap(Op1, Op2);
+  if (!Op1->isReg() || !Op2->isImm() || Op2->getImm() != 1)
+    return AMDGPU::NoRegister;
----------------
Op2 doesn't need to be an immediate 1, it just needs to match the selected operand


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Comment at: lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp:186-190
+  MachineInstr *Andn2 = BuildMI(MBB, *And, And->getDebugLoc(),
+                                TII->get(Andn2Opc),
+                                And->getOperand(0).getReg())
+                                  .addReg(ExecReg)
+                                  .addReg(CCReg, CC->getSubReg());
----------------
Weird formatting


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Comment at: lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp:237-240
+      RecalcRegs.insert(Reg);
+      RecalcRegs.insert(AMDGPU::VCC_LO);
+      RecalcRegs.insert(AMDGPU::VCC_HI);
+      RecalcRegs.insert(AMDGPU::SCC);
----------------
Why is just Reg itself OK? Doesn't this need to use the reg alias iterator?


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Comment at: test/CodeGen/AMDGPU/optimize-negated-cond-exec-masking.mir:420-423
+registers:
+  - { id: 0, class: sreg_64_xexec }
+  - { id: 1, class: vreg_128 }
+  - { id: 2, class: sreg_64_xexec }
----------------
You can drop all of the register sections


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Comment at: test/CodeGen/AMDGPU/optimize-negated-cond.ll:3
+
+; GCN: BB0_1:
+; GCN:   v_cmp_eq_u32_e64 [[CC:[^,]+]], s{{[0-9]+}}, 0
----------------
Function label


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Comment at: test/CodeGen/AMDGPU/optimize-negated-cond.ll:10
+; GCN:   s_cbranch_vccz BB0_4
+define amdgpu_kernel void @test(float addrspace(1)* %arg1) {
+bb:
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Can this be reduced?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D55402/new/

https://reviews.llvm.org/D55402