[PATCH] D55297: [DemandedBits][BDCE] Support vectors of integers

Thu Dec 6 04:27:02 PST 2018

RKSimon added inline comments.

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Comment at: test/Analysis/DemandedBits/vectors.ll:7
+; CHECK-DAG: DemandedBits: 0xff00 for   %z = or <2 x i32> %x, %y
+; CHECK-DAG: DemandedBits: 0xff for   %u = lshr <2 x i32> %z, <i32 8, i32 8>
+; CHECK-DAG: DemandedBits: 0xff for   %r = trunc <2 x i32> %u to <2 x i8>
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nikic wrote:
> hfinkel wrote:
> > I'm missing something here. Shouldn't there be two groups of demanded bits here, one group per vector lane, so that the overall demanded bits looks something like: 0x000000ff000000ff?
> > 
> The demanded bits are tracked for all vector lanes together. A bit is demanded if it is demanded in any of the vector lanes.
> 
> Other passes that do similar things (computeKnownBits in ValueTracking and SimplifyDemandedBits in InstCombine) take the same approach. I assume that because it's usually not worth the additional computational cost (and in this case also memory usage) to track bits for individual lanes. It also simplifies things for consumers of the analysis, as it allows treating scalar and vectors in the same way.
I raised https://bugs.llvm.org/show_bug.cgi?id=36319 about at least adding the same DemandedElts argument support to ValueTracking that we have with the SelectionDAG computeKnownBits/ComputeNumSignBits equivalents.

I have toyed with the idea of adding a DemandedElts argument to SimplifyDemandedBits as well but haven't pursued it yet (so not completely "per bit" but at least limited to shared demandedbits from the vector elements we care about).

Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D55297/new/

https://reviews.llvm.org/D55297