[PATCH] D55297: [DemandedBits][BDCE] Support vectors of integers

[Hal Finkel via Phabricator via llvm-commits]

hfinkel added inline comments.


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Comment at: test/Analysis/DemandedBits/vectors.ll:7
+; CHECK-DAG: DemandedBits: 0xff00 for   %z = or <2 x i32> %x, %y
+; CHECK-DAG: DemandedBits: 0xff for   %u = lshr <2 x i32> %z, <i32 8, i32 8>
+; CHECK-DAG: DemandedBits: 0xff for   %r = trunc <2 x i32> %u to <2 x i8>
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I'm missing something here. Shouldn't there be two groups of demanded bits here, one group per vector lane, so that the overall demanded bits looks something like: 0x000000ff000000ff?



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  rL LLVM

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  https://reviews.llvm.org/D55297/new/

https://reviews.llvm.org/D55297