[PATCH] D55301: RegAlloc: Allow targets to split register allocation

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
arsenm added reviewers: MatzeB, qcolombet, rampitec, scott.linder.
Herald added subscribers: tpr, mgorny, nhaehnle, wdng, jvesely.

AMDGPU normally spills SGPRs to VGPRs. Previously, since all register
classes are handled at the same time, this was problematic. We don't
know ahead of time how many registers will be needed to be reserved to
handle the spilling. If no VGPRs were left for spilling, we would have
to try to spill to memory. If the spilled SGPRs were required for exec
mask manipulation, it is highly problematic because the lanes active
at the point of spill are not necessarily the same as at the restore
point.

      

Avoid this problem by fully allocating SGPRs in a separate regalloc
run from VGPRs. This way we know the exact number of VGPRs needed, and
can reserve them for a second run.  This fixes the most serious
issues, but it is still possible using inline asm to make all VGPRs
unavailable. Start erroring in the case where we ever would require
memory for an SGPR spill.

      

This is implemented by giving each regalloc pass a callback which
 reports if a register class should be handled or not. A few passes
need some small changes to deal with leftover virtual registers.

      

In the AMDGPU implementation, a new pass is introduced to take the
place of PrologEpilogInserter for SGPR spills emitted during the first
run.

      

One disadvantage of this is currently StackSlotColoring is no longer
used for SGPR spills. It would need to be run again, which will
require more work.

      

Error if the standard -regalloc option is used. Introduce new separate
-sgpr-regalloc and -vgpr-regalloc flags, so the two runs can be
controlled individually. PBQB is not currently supported, so this also
prevents using the unhandled allocator.


https://reviews.llvm.org/D55301

Files:
  include/llvm/CodeGen/Passes.h
  include/llvm/CodeGen/RegAllocCommon.h
  include/llvm/CodeGen/RegAllocRegistry.h
  include/llvm/CodeGen/TargetFrameLowering.h
  lib/CodeGen/LiveIntervals.cpp
  lib/CodeGen/RegAllocBase.cpp
  lib/CodeGen/RegAllocBase.h
  lib/CodeGen/RegAllocBasic.cpp
  lib/CodeGen/RegAllocFast.cpp
  lib/CodeGen/RegAllocGreedy.cpp
  lib/CodeGen/TargetFrameLoweringImpl.cpp
  lib/Target/AMDGPU/AMDGPU.h
  lib/Target/AMDGPU/AMDGPUCallingConv.td
  lib/Target/AMDGPU/AMDGPURegisterInfo.cpp
  lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
  lib/Target/AMDGPU/CMakeLists.txt
  lib/Target/AMDGPU/SIFrameLowering.cpp
  lib/Target/AMDGPU/SIFrameLowering.h
  lib/Target/AMDGPU/SILowerSGPRSpills.cpp
  lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
  lib/Target/AMDGPU/SIMachineFunctionInfo.h
  lib/Target/AMDGPU/SIRegisterInfo.cpp
  lib/Target/AMDGPU/SIRegisterInfo.h
  test/CodeGen/AMDGPU/callee-frame-setup.ll
  test/CodeGen/AMDGPU/callee-special-input-sgprs.ll
  test/CodeGen/AMDGPU/callee-special-input-vgprs.ll
  test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll
  test/CodeGen/AMDGPU/debug-value2.ll
  test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll
  test/CodeGen/AMDGPU/sgpr-regalloc-flags.ll
  test/CodeGen/AMDGPU/sgpr-spill-no-vgprs.ll
  test/CodeGen/AMDGPU/sgpr-spill-wrong-stack-id.mir
  test/CodeGen/AMDGPU/si-spill-sgpr-stack.ll
  test/CodeGen/AMDGPU/sibling-call.ll
  test/CodeGen/AMDGPU/spill-csr-frame-ptr-reg-copy.ll
  test/CodeGen/AMDGPU/spill-empty-live-interval.mir
  test/CodeGen/AMDGPU/spill-scavenge-offset.ll
  test/CodeGen/AMDGPU/stack-slot-color-sgpr-vgpr-spills.mir

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