[PATCH] D55241: AMDGPU: Should always start from the first register in VGPR indexing.

[Changpeng Fang via Phabricator via llvm-commits]

cfang created this revision.
cfang added reviewers: arsenm, msearles, rampitec.
Herald added subscribers: arphaman, t-tye, tpr, dstuttard, yaxunl, nhaehnle, wdng, jvesely, kzhuravl.

SunReg should always be AMDGPU::sub0. The 8-bit m0 field for the index is unsigned.
We can guarantee the index non-negative (if the program  itself is correct) only when we 
start from the very first register in the vector.

The original optimization shifts the base to AMDGPU::sub0 + Offset, which leads to the situation
that the index could be negative to address the registers to the left of the base (Offset). Thus the 
optimization is invalid.


https://reviews.llvm.org/D55241

Files:
  lib/Target/AMDGPU/SIISelLowering.cpp
  test/CodeGen/AMDGPU/indirect-addressing-si-pregfx9.ll
  test/CodeGen/AMDGPU/indirect-addressing-si.ll

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