[llvm] r348117 - [RISCV] Fix test/MC/Disassembler/RISCV/invalid-instruction.txt after rL347988

[Alex Bradbury via llvm-commits]

Author: asb
Date: Mon Dec  3 02:35:46 2018
New Revision: 348117

URL: http://llvm.org/viewvc/llvm-project?rev=348117&view=rev
Log:
[RISCV] Fix test/MC/Disassembler/RISCV/invalid-instruction.txt after rL347988

The test for [0x00 0x00] failed due to the introduction of c.unimp.

This particular test is unnecessary now that c.unimp was defined (and is 
tested in test/MC/RISCV/rv32c-valid.s).

Modified:
    llvm/trunk/test/MC/Disassembler/RISCV/invalid-instruction.txt

Modified: llvm/trunk/test/MC/Disassembler/RISCV/invalid-instruction.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/RISCV/invalid-instruction.txt?rev=348117&r1=348116&r2=348117&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/RISCV/invalid-instruction.txt (original)
+++ llvm/trunk/test/MC/Disassembler/RISCV/invalid-instruction.txt Mon Dec  3 02:35:46 2018
@@ -4,10 +4,6 @@
 # Test generated by a LLVM MC Disassembler Protocol Buffer Fuzzer
 # for the RISC-V assembly language.
 
-# This should not decode as c.addi4spn with 0 imm when compression is enabled.
-[0x00 0x00]
-# CHECK: warning: invalid instruction encoding
-
 # This should not decode as c.addi16sp with 0 imm when compression is enabled.
 [0x01 0x61]
 # CHECK: warning: invalid instruction encoding