[llvm] r348111 - [GlobalISel] Fix test irtranslator-stackprotect-check.ll

[Petr Pavlu via llvm-commits]

Author: petr.pavlu
Date: Mon Dec  3 01:28:28 2018
New Revision: 348111

URL: http://llvm.org/viewvc/llvm-project?rev=348111&view=rev
Log:
[GlobalISel] Fix test irtranslator-stackprotect-check.ll

Fix for commit r347862. Use correct AArch64 triple in test
CodeGen/AArch64/GlobalISel/irtranslator-stackprotect-check.ll.

Modified:
    llvm/trunk/test/CodeGen/AArch64/GlobalISel/irtranslator-stackprotect-check.ll

Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/irtranslator-stackprotect-check.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/irtranslator-stackprotect-check.ll?rev=348111&r1=348110&r2=348111&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/irtranslator-stackprotect-check.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/irtranslator-stackprotect-check.ll Mon Dec  3 01:28:28 2018
@@ -5,7 +5,7 @@
 ; both prologue and epilogue instrumentation because GlobalISel does not have
 ; the same epilogue insertion/optimization as SelectionDAG.
 
-target triple = "armv8-arm-none-eabi"
+target triple = "aarch64-none-unknown-eabi"
 
 define void @foo() ssp {
 ; CHECK-LABEL: entry:
@@ -27,23 +27,23 @@ define void @foo() ssp {
 
 ; CHECK-MIR: bb.1.entry:
 ; CHECK-MIR:   %0:_(p0) = G_FRAME_INDEX %stack.0.StackGuardSlot
-; CHECK-MIR-NEXT:   %1:gpr(p0) = LOAD_STACK_GUARD :: (dereferenceable invariant load 4 from @__stack_chk_guard)
-; CHECK-MIR-NEXT:   %2:gpr(p0) = LOAD_STACK_GUARD :: (dereferenceable invariant load 4 from @__stack_chk_guard)
-; CHECK-MIR-NEXT:   G_STORE %2(p0), %0(p0) :: (volatile store 4 into %stack.0.StackGuardSlot, align 8)
+; CHECK-MIR-NEXT:   %1:gpr64sp(p0) = LOAD_STACK_GUARD :: (dereferenceable invariant load 8 from @__stack_chk_guard)
+; CHECK-MIR-NEXT:   %2:gpr64sp(p0) = LOAD_STACK_GUARD :: (dereferenceable invariant load 8 from @__stack_chk_guard)
+; CHECK-MIR-NEXT:   G_STORE %2(p0), %0(p0) :: (volatile store 8 into %stack.0.StackGuardSlot)
 ; CHECK-MIR-NEXT:   %3:_(p0) = G_FRAME_INDEX %stack.1.buf
-; CHECK-MIR-NEXT:   %4:gpr(p0) = LOAD_STACK_GUARD :: (dereferenceable invariant load 4 from @__stack_chk_guard)
-; CHECK-MIR-NEXT:   %5:_(p0) = G_LOAD %0(p0) :: (volatile load 4 from %ir.StackGuardSlot)
+; CHECK-MIR-NEXT:   %4:gpr64sp(p0) = LOAD_STACK_GUARD :: (dereferenceable invariant load 8 from @__stack_chk_guard)
+; CHECK-MIR-NEXT:   %5:_(p0) = G_LOAD %0(p0) :: (volatile load 8 from %ir.StackGuardSlot)
 ; CHECK-MIR-NEXT:   %6:_(s1) = G_ICMP intpred(eq), %4(p0), %5
 ; CHECK-MIR-NEXT:   G_BRCOND %6(s1), %bb.2
 ; CHECK-MIR-NEXT:   G_BR %bb.3
 ;
 ; CHECK-MIR: bb.2.SP_return:
-; CHECK-MIR-NEXT:   BX_RET 14, $noreg
+; CHECK-MIR-NEXT:   RET_ReallyLR
 ;
 ; CHECK-MIR: bb.3.CallStackCheckFailBlk:
-; CHECK-MIR-NEXT:   ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def $sp, implicit $sp
-; CHECK-MIR-NEXT:   BL @__stack_chk_fail, csr_aapcs, implicit-def $lr, implicit $sp
-; CHECK-MIR-NEXT:   ADJCALLSTACKUP 0, 0, 14, $noreg, implicit-def $sp, implicit $sp
+; CHECK-MIR-NEXT:   ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
+; CHECK-MIR-NEXT:   BL @__stack_chk_fail, csr_aarch64_aapcs, implicit-def $lr, implicit $sp
+; CHECK-MIR-NEXT:   ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
 entry:
   %buf = alloca [8 x i8], align 1
   ret void