[llvm] r348110 - [ARM] FP16: support vld1.16 for vector loads with post-increment

[Sjoerd Meijer via llvm-commits]

Author: sjoerdmeijer
Date: Mon Dec  3 00:26:34 2018
New Revision: 348110

URL: http://llvm.org/viewvc/llvm-project?rev=348110&view=rev
Log:
[ARM] FP16: support vld1.16 for vector loads with post-increment

Differential Revision: https://reviews.llvm.org/D55112

Added:
    llvm/trunk/test/CodeGen/ARM/fp16-vld.ll
Modified:
    llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=348110&r1=348109&r2=348110&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Mon Dec  3 00:26:34 2018
@@ -1763,12 +1763,14 @@ void ARMDAGToDAGISel::SelectVLD(SDNode *
   default: llvm_unreachable("unhandled vld type");
     // Double-register operations:
   case MVT::v8i8:  OpcodeIndex = 0; break;
+  case MVT::v4f16:
   case MVT::v4i16: OpcodeIndex = 1; break;
   case MVT::v2f32:
   case MVT::v2i32: OpcodeIndex = 2; break;
   case MVT::v1i64: OpcodeIndex = 3; break;
     // Quad-register operations:
   case MVT::v16i8: OpcodeIndex = 0; break;
+  case MVT::v8f16:
   case MVT::v8i16: OpcodeIndex = 1; break;
   case MVT::v4f32:
   case MVT::v4i32: OpcodeIndex = 2; break;

Added: llvm/trunk/test/CodeGen/ARM/fp16-vld.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fp16-vld.ll?rev=348110&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fp16-vld.ll (added)
+++ llvm/trunk/test/CodeGen/ARM/fp16-vld.ll Mon Dec  3 00:26:34 2018
@@ -0,0 +1,48 @@
+; RUN: llc -asm-verbose=false < %s | FileCheck %s
+
+target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
+target triple = "armv8.2a-arm-unknown-eabihf"
+
+define dso_local void @vec8(half* nocapture readonly %V, i32 %N) local_unnamed_addr #0 {
+; CHECK:      .LBB0_1:
+; CHECK-NEXT: vld1.16 {d16, d17}, [r0]!
+; CHECK-NEXT: subs r1, r1, #8
+; CHECK-NEXT: bne .LBB0_1
+entry:
+  br label %vector.body
+
+vector.body:
+  %index = phi i32 [ 0, %entry ], [ %index.next, %vector.body ]
+  %0 = getelementptr inbounds half, half* %V, i32 %index
+  %1 = bitcast half* %0 to <8 x half>*
+  %wide.load = load volatile <8 x half>, <8 x half>* %1, align 2
+  %index.next = add i32 %index, 8
+  %cmp = icmp eq i32 %index.next, %N
+  br i1 %cmp, label %byeblock, label %vector.body
+
+byeblock:
+  ret void
+}
+
+define dso_local void @vec4(half* nocapture readonly %V, i32 %N) local_unnamed_addr #0 {
+; CHECK:      .LBB1_1:
+; CHECK-NEXT: vld1.16 {d16}, [r0]!
+; CHECK-NEXT: subs r1, r1, #4
+; CHECK-NEXT:	bne	.LBB1_1
+entry:
+  br label %vector.body
+
+vector.body:
+  %index = phi i32 [ 0, %entry ], [ %index.next, %vector.body ]
+  %0 = getelementptr inbounds half, half* %V, i32 %index
+  %1 = bitcast half* %0 to <4 x half>*
+  %wide.load = load volatile <4 x half>, <4 x half>* %1, align 2
+  %index.next = add i32 %index, 4
+  %cmp = icmp eq i32 %index.next, %N
+  br i1 %cmp, label %byeblock, label %vector.body
+
+byeblock:
+  ret void
+}
+
+attributes #0 = { norecurse nounwind readonly "no-infs-fp-math"="true" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "target-cpu"="generic" "target-features"="+armv8.2-a,+fullfp16,+strict-align,-thumb-mode" "unsafe-fp-math"="true" "use-soft-float"="false" }