[PATCH] D55059: [ARM] FP16: constant initialised v4f16 and v8f16 vectors

[Oliver Stannard via Phabricator via llvm-commits]

olista01 added inline comments.


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Comment at: lib/Target/ARM/ARMInstrNEON.td:7145
 let Predicates = [IsLE] in {
+  def : Pat<(v4f16 (bitconvert (v4i16 DPR:$src))), (v4f16 DPR:$src)>;
   def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (v4i16 DPR:$src)>;
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There are still a lot of combinations of types missing here, I think it would be better to add all of them at once. It might also be better to re-write all of these patterns as a pair of tablegen foreach loops, so that we don't miss any combinations.


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Comment at: lib/Target/ARM/ARMInstrNEON.td:7228
   def : Pat<(v2i32 (bitconvert (f64   DPR:$src))), (VREV64d32 DPR:$src)>;
+  def : Pat<(v4f16 (bitconvert (v4i16 DPR:$src))), (VREV64d16 DPR:$src)>;
   def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (VREV64d16 DPR:$src)>;
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Why does this need a VREV? All of the other cases where the lane widths are the same are no-ops for BE and LE.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D55059/new/

https://reviews.llvm.org/D55059