[llvm] r347534 - Revert "[PowerPC] Fix inconsistent ImmMustBeMultipleOf for same instruction"
Kang Zhang via llvm-commits
llvm-commits at lists.llvm.org
Sun Nov 25 23:15:31 PST 2018
Author: zhangkang
Date: Sun Nov 25 23:15:31 2018
New Revision: 347534
URL: http://llvm.org/viewvc/llvm-project?rev=347534&view=rev
Log:
Revert "[PowerPC] Fix inconsistent ImmMustBeMultipleOf for same instruction"
This reverts commits r347532. Forget add the option
-mtriple powerpc64-unknown-linux-gnu. So other platform is error except
for PowerPC.
Removed:
llvm/trunk/test/CodeGen/PowerPC/convert-rr-to-ri-p9-vector.mir
Modified:
llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp
Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp?rev=347534&r1=347533&r2=347534&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp Sun Nov 25 23:15:31 2018
@@ -2984,10 +2984,8 @@ bool PPCInstrInfo::instrHasImmForm(const
if (PostRA) {
if (isVFReg(MI.getOperand(0).getReg()))
III.ImmOpcode = PPC::LXSSP;
- else {
+ else
III.ImmOpcode = PPC::LFS;
- III.ImmMustBeMultipleOf = 1;
- }
break;
}
LLVM_FALLTHROUGH;
@@ -2998,10 +2996,8 @@ bool PPCInstrInfo::instrHasImmForm(const
if (PostRA) {
if (isVFReg(MI.getOperand(0).getReg()))
III.ImmOpcode = PPC::LXSD;
- else {
+ else
III.ImmOpcode = PPC::LFD;
- III.ImmMustBeMultipleOf = 1;
- }
break;
}
LLVM_FALLTHROUGH;
@@ -3016,10 +3012,8 @@ bool PPCInstrInfo::instrHasImmForm(const
if (PostRA) {
if (isVFReg(MI.getOperand(0).getReg()))
III.ImmOpcode = PPC::STXSSP;
- else {
+ else
III.ImmOpcode = PPC::STFS;
- III.ImmMustBeMultipleOf = 1;
- }
break;
}
LLVM_FALLTHROUGH;
@@ -3030,10 +3024,8 @@ bool PPCInstrInfo::instrHasImmForm(const
if (PostRA) {
if (isVFReg(MI.getOperand(0).getReg()))
III.ImmOpcode = PPC::STXSD;
- else {
+ else
III.ImmOpcode = PPC::STFD;
- III.ImmMustBeMultipleOf = 1;
- }
break;
}
LLVM_FALLTHROUGH;
Removed: llvm/trunk/test/CodeGen/PowerPC/convert-rr-to-ri-p9-vector.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/convert-rr-to-ri-p9-vector.mir?rev=347533&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/convert-rr-to-ri-p9-vector.mir (original)
+++ llvm/trunk/test/CodeGen/PowerPC/convert-rr-to-ri-p9-vector.mir (removed)
@@ -1,161 +0,0 @@
-# RUN: llc -start-after ppc-mi-peepholes -ppc-late-peephole -mcpu=pwr9 %s -o - | FileCheck %s
-
----
-name: testLXSSPX
-alignment: 4
-exposesReturnsTwice: false
-legalized: false
-regBankSelected: false
-selected: false
-tracksRegLiveness: true
-registers:
- - { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' }
- - { id: 1, class: g8rc, preferred-register: '' }
- - { id: 2, class: gprc_and_gprc_nor0, preferred-register: '' }
- - { id: 3, class: gprc, preferred-register: '' }
- - { id: 4, class: g8rc, preferred-register: '' }
- - { id: 5, class: g8rc, preferred-register: '' }
- - { id: 6, class: g8rc, preferred-register: '' }
- - { id: 7, class: vssrc, preferred-register: '' }
- - { id: 8, class: gprc, preferred-register: '' }
- - { id: 9, class: g8rc, preferred-register: '' }
- - { id: 10, class: g8rc, preferred-register: '' }
- - { id: 11, class: g8rc, preferred-register: '' }
- - { id: 12, class: vssrc, preferred-register: '' }
- - { id: 13, class: vssrc, preferred-register: '' }
-liveins:
- - { reg: '$x3', virtual-reg: '%0' }
- - { reg: '$x4', virtual-reg: '%1' }
-body: |
- bb.0.entry:
- liveins: $x3, $x4
-
- %1 = COPY $x4
- %0 = COPY $x3
- %2 = COPY %1.sub_32
- %3 = ADDI %2, 1
- %5 = IMPLICIT_DEF
- %4 = INSERT_SUBREG %5, killed %3, 1
- %6 = LI8 97
- %7 = LXSSPX %0, killed %6, implicit $rm
- ; CHECK: lfs [[REG1:[0-9]+]], 97(3)
- %8 = ADDI %2, 2
- %10 = IMPLICIT_DEF
- %9 = INSERT_SUBREG %10, killed %8, 1
- %11 = LI8 -92
- %12 = LXSSPX %0, killed %11, implicit $rm
- ; CHECK-NEXT: lfs [[REG2:[0-9]+]], -92(3)
- %13 = XSADDSP killed %7, killed %12
- ; CHECK-NEXT: xsaddsp {{[0-9]+}}, [[REG1]], [[REG2]]
- $f1 = COPY %13
- BLR8 implicit $lr8, implicit $rm, implicit $f1
-...
-
-
----
-name: testLXSDX
-tracksRegLiveness: true
-registers:
- - { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' }
- - { id: 1, class: g8rc, preferred-register: '' }
- - { id: 2, class: gprc_and_gprc_nor0, preferred-register: '' }
- - { id: 3, class: gprc, preferred-register: '' }
- - { id: 4, class: g8rc, preferred-register: '' }
- - { id: 5, class: g8rc, preferred-register: '' }
- - { id: 6, class: g8rc, preferred-register: '' }
- - { id: 7, class: vsfrc, preferred-register: '' }
- - { id: 8, class: gprc, preferred-register: '' }
- - { id: 9, class: g8rc, preferred-register: '' }
- - { id: 10, class: g8rc, preferred-register: '' }
- - { id: 11, class: g8rc, preferred-register: '' }
- - { id: 12, class: vsfrc, preferred-register: '' }
- - { id: 13, class: vsfrc, preferred-register: '' }
-liveins:
- - { reg: '$x3', virtual-reg: '%0' }
- - { reg: '$x4', virtual-reg: '%1' }
-body: |
- bb.0.entry:
- liveins: $x3, $x4
-
- %1 = COPY $x4
- %0 = COPY $x3
- %2 = COPY %1.sub_32
- %3 = ADDI %2, 1
- %5 = IMPLICIT_DEF
- %4 = INSERT_SUBREG %5, killed %3, 1
- %6 = LI8 99
- %7 = LXSDX %0, killed %6, implicit $rm
- ; CHECK: lfd [[REG1:[0-9]+]], 99(3)
- %8 = ADDI %2, 2
- %10 = IMPLICIT_DEF
- %9 = INSERT_SUBREG %10, killed %8, 1
- %11 = LI8 -120
- %12 = LXSDX %0, killed %11, implicit $rm
- ; CHECK-NEXT: lfd [[REG2:[0-9]+]], -120(3)
- %13 = XSADDDP killed %7, killed %12, implicit $rm
- ; CHECK-NEXT: xsadddp {{[0-9]+}}, [[REG1]], [[REG2]]
- $f1 = COPY %13
- BLR8 implicit $lr8, implicit $rm, implicit $f1
-...
-
-
----
-name: testSTXSSPX
-alignment: 4
-exposesReturnsTwice: false
-legalized: false
-regBankSelected: false
-selected: false
-tracksRegLiveness: true
-registers:
- - { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' }
- - { id: 1, class: vssrc, preferred-register: '' }
- - { id: 2, class: g8rc, preferred-register: '' }
- - { id: 3, class: g8rc, preferred-register: '' }
-liveins:
- - { reg: '$x3', virtual-reg: '%0' }
- - { reg: '$f1', virtual-reg: '%1' }
- - { reg: '$x5', virtual-reg: '%2' }
-body: |
- bb.0.entry:
- liveins: $x3, $f1, $x5
-
- %2 = COPY $x5
- %1 = COPY $f1
- %0 = COPY $x3
- %3 = LI8 443
- STXSSPX %1, %0, killed %3, implicit $rm
- ; CHECK: stfs {{[0-9]+}}, 443(3)
- BLR8 implicit $lr8, implicit $rm
-...
-
-
----
-name: testSTXSDX
-alignment: 4
-exposesReturnsTwice: false
-legalized: false
-regBankSelected: false
-selected: false
-tracksRegLiveness: true
-registers:
- - { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' }
- - { id: 1, class: vsfrc, preferred-register: '' }
- - { id: 2, class: g8rc, preferred-register: '' }
- - { id: 3, class: g8rc, preferred-register: '' }
-liveins:
- - { reg: '$x3', virtual-reg: '%0' }
- - { reg: '$f1', virtual-reg: '%1' }
- - { reg: '$x5', virtual-reg: '%2' }
-body: |
- bb.0.entry:
- liveins: $x3, $f1, $x5
-
- %2 = COPY $x5
- %1 = COPY $f1
- %0 = COPY $x3
- %3 = LI8 7
- STXSDX %1, %0, killed %3, implicit $rm
- ; CHECK: stfd {{[0-9]+}}, 7(3)
- BLR8 implicit $lr8, implicit $rm
-...
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