[PATCH] D54853: [ARM][MC] Move information about variadic register defs into tablegen

[Oliver Stannard via Phabricator via llvm-commits]

olista01 created this revision.
olista01 added reviewers: t.p.northover, rengolin.
Herald added subscribers: chrib, kristof.beyls, javed.absar.

Currently, variadic operands on an MCInst are assumed to be uses,
because they come after the defs. However, this is not always the case,
for example the Arm/Thumb LDM instructions write to a variable number of
registers.

This adds a property of instruction definitions which can be used to
mark variadic operands as defs. This only affects MCInst, because
MachineInstruction already tracks use/def per operand in each instance
of the instruction, so can already represent this.

This property can then be checked in MCInstrDesc, allowing us to remove
some special cases in ARMAsmParser::isITBlockTerminator.


Repository:
  rL LLVM

https://reviews.llvm.org/D54853

Files:
  include/llvm/MC/MCInstrDesc.h
  include/llvm/Target/Target.td
  lib/MC/MCInstrDesc.cpp
  lib/Target/ARM/ARMInstrInfo.td
  lib/Target/ARM/ARMInstrThumb.td
  lib/Target/ARM/ARMInstrThumb2.td
  lib/Target/ARM/AsmParser/ARMAsmParser.cpp
  utils/TableGen/CodeGenInstruction.cpp
  utils/TableGen/CodeGenInstruction.h
  utils/TableGen/InstrDocsEmitter.cpp
  utils/TableGen/InstrInfoEmitter.cpp

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