[PATCH] D54725: [SelectionDAG] Compute known bits and num sign bits for live out vector registers. Use it to add AssertZExt/AssertSExt in the live in basic blocks

[Craig Topper via Phabricator via llvm-commits]

craig.topper updated this revision to Diff 174718.
craig.topper added a comment.

Update comment


https://reviews.llvm.org/D54725

Files:
  lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
  lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
  test/CodeGen/X86/vector-mul.ll

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