[llvm] r347268 - [X86] Rename combineVSZext->combineExtendVectorInreg. NFC

[Craig Topper via llvm-commits]

Author: ctopper
Date: Mon Nov 19 14:18:47 2018
New Revision: 347268

URL: http://llvm.org/viewvc/llvm-project?rev=347268&view=rev
Log:
[X86] Rename combineVSZext->combineExtendVectorInreg. NFC

Now that we no longer have target specific vector extend nodes let's make the function name match the nodes we do use.

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=347268&r1=347267&r2=347268&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon Nov 19 14:18:47 2018
@@ -40494,9 +40494,9 @@ static SDValue combineSub(SDNode *N, Sel
   return combineAddOrSubToADCOrSBB(N, DAG);
 }
 
-static SDValue combineVSZext(SDNode *N, SelectionDAG &DAG,
-                             TargetLowering::DAGCombinerInfo &DCI,
-                             const X86Subtarget &Subtarget) {
+static SDValue combineExtendVectorInreg(SDNode *N, SelectionDAG &DAG,
+                                        TargetLowering::DAGCombinerInfo &DCI,
+                                        const X86Subtarget &Subtarget) {
   if (DCI.isBeforeLegalize())
     return SDValue();
 
@@ -40928,7 +40928,7 @@ SDValue X86TargetLowering::PerformDAGCom
     return combineVectorShiftImm(N, DAG, DCI, Subtarget);
   case ISD::SIGN_EXTEND_VECTOR_INREG:
   case ISD::ZERO_EXTEND_VECTOR_INREG:
-    return combineVSZext(N, DAG, DCI, Subtarget);
+    return combineExtendVectorInreg(N, DAG, DCI, Subtarget);
   case X86ISD::PINSRB:
   case X86ISD::PINSRW:      return combineVectorInsert(N, DAG, DCI, Subtarget);
   case X86ISD::SHUFP:       // Handle all target specific shuffles