[PATCH] D54623: [MSP430] Optimize srl/sra in case of A >> (8 + N)

[Eli Friedman via Phabricator via llvm-commits]

efriedma added inline comments.


================
Comment at: lib/Target/MSP430/MSP430ISelLowering.cpp:954
+    unsigned ExtOpc =
+        Opc == ISD::SRA ? ISD::SIGN_EXTEND_INREG : ISD::ZERO_EXTEND;
+    Victim = DAG.getNode(ExtOpc, dl, VT, Victim, DAG.getValueType(MVT::i8));
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I'm confused how the ZERO_EXTEND case works; you aren't even passing the right number of operands for a ZERO_EXTEND.  (There is no ZERO_EXTEND_INREG because it's equivalent to an AND with the appropriate immediate.  There's a helper function SelectionDAG::getZeroExtendInReg() to generate that for you.)


Repository:
  rL LLVM

https://reviews.llvm.org/D54623