[llvm] r347027 - AMDGPU: Fix analyzeBranch failing with pseudoterminators
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Thu Nov 15 21:03:02 PST 2018
Author: arsenm
Date: Thu Nov 15 21:03:02 2018
New Revision: 347027
URL: http://llvm.org/viewvc/llvm-project?rev=347027&view=rev
Log:
AMDGPU: Fix analyzeBranch failing with pseudoterminators
If a block had one of the _term instructions used for gluing
exec modifying instructions to the end of the block,
analyzeBranch would fail, preventing the verifier from catching
a broken successor list.
Added:
llvm/trunk/test/CodeGen/AMDGPU/verifier-pseudo-terminators.mir
Modified:
llvm/trunk/lib/Target/AMDGPU/SIInsertSkips.cpp
llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
llvm/trunk/lib/Target/AMDGPU/SIInstructions.td
Modified: llvm/trunk/lib/Target/AMDGPU/SIInsertSkips.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInsertSkips.cpp?rev=347027&r1=347026&r2=347027&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInsertSkips.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIInsertSkips.cpp Thu Nov 15 21:03:02 2018
@@ -476,7 +476,7 @@ bool SIInsertSkips::runOnMachineFunction
kill(MI);
if (ExecBranchStack.empty()) {
- if (skipIfDead(MI, *NextBB)) {
+ if (NextBB != BE && skipIfDead(MI, *NextBB)) {
HaveSkipBlock = true;
NextBB = std::next(BI);
BE = MF.end();
Modified: llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp?rev=347027&r1=347026&r2=347027&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp Thu Nov 15 21:03:02 2018
@@ -1632,7 +1632,34 @@ bool SIInstrInfo::analyzeBranch(MachineB
SmallVectorImpl<MachineOperand> &Cond,
bool AllowModify) const {
MachineBasicBlock::iterator I = MBB.getFirstTerminator();
- if (I == MBB.end())
+ auto E = MBB.end();
+ if (I == E)
+ return false;
+
+ // Skip over the instructions that are artificially terminators for special
+ // exec management.
+ while (I != E && !I->isBranch() && !I->isReturn() &&
+ I->getOpcode() != AMDGPU::SI_MASK_BRANCH) {
+ switch (I->getOpcode()) {
+ case AMDGPU::SI_MASK_BRANCH:
+ case AMDGPU::S_MOV_B64_term:
+ case AMDGPU::S_XOR_B64_term:
+ case AMDGPU::S_ANDN2_B64_term:
+ break;
+ case AMDGPU::SI_IF:
+ case AMDGPU::SI_ELSE:
+ case AMDGPU::SI_KILL_I1_TERMINATOR:
+ case AMDGPU::SI_KILL_F32_COND_IMM_TERMINATOR:
+ // FIXME: It's messy that these need to be considered here at all.
+ return true;
+ default:
+ llvm_unreachable("unexpected non-branch terminator inst");
+ }
+
+ ++I;
+ }
+
+ if (I == E)
return false;
if (I->getOpcode() != AMDGPU::SI_MASK_BRANCH)
Modified: llvm/trunk/lib/Target/AMDGPU/SIInstructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstructions.td?rev=347027&r1=347026&r2=347027&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstructions.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIInstructions.td Thu Nov 15 21:03:02 2018
@@ -247,7 +247,7 @@ def SI_LOOP : CFPseudoInstSI <
(outs), (ins SReg_64:$saved, brtarget:$target),
[(AMDGPUloop i64:$saved, bb:$target)], 1, 1> {
let Size = 8;
- let isBranch = 0;
+ let isBranch = 1;
let hasSideEffects = 1;
}
@@ -307,6 +307,7 @@ def SI_ILLEGAL_COPY : SPseudoInstSI <
def SI_BR_UNDEF : SPseudoInstSI <(outs), (ins sopp_brtarget:$simm16)> {
let isTerminator = 1;
let usesCustomInserter = 1;
+ let isBranch = 1;
}
def SI_PS_LIVE : PseudoInstSI <
Added: llvm/trunk/test/CodeGen/AMDGPU/verifier-pseudo-terminators.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/verifier-pseudo-terminators.mir?rev=347027&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/verifier-pseudo-terminators.mir (added)
+++ llvm/trunk/test/CodeGen/AMDGPU/verifier-pseudo-terminators.mir Thu Nov 15 21:03:02 2018
@@ -0,0 +1,23 @@
+# RUN: not llc -march=amdgcn -run-pass=verify %s 2>&1 | FileCheck %s
+# Make sure that mismatched successors are caught when a _term
+# instruction is used
+
+# CHECK: *** Bad machine code: MBB exits via unconditional branch but the CFG successor doesn't match the actual successor! ***
+
+---
+name: verifier_pseudo_terminators
+body: |
+ bb.0:
+ successors: %bb.1
+
+ %0:sreg_64 = S_XOR_B64_term undef %1:sreg_64, undef %2:sreg_64, implicit-def $scc
+ $exec = S_MOV_B64_term %0
+ S_BRANCH %bb.2
+
+ bb.1:
+ S_SETPC_B64_return undef $sgpr30_sgpr31
+
+ bb.2:
+ S_SETPC_B64_return undef $sgpr30_sgpr31
+
+...
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