[PATCH] D54218: [MachineScheduler] Bias physical register immediate assignments

[Quentin Colombet via Phabricator via llvm-commits]

qcolombet added a comment.

I see a few checks that weaken the check (e.g., -next replaced by regular checks).
Is this expected and why?



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Comment at: llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll:20
 ; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}
-; GCN-DAG: s_mov_b32 [[CONSTREG:s[0-9]+]], 0x40a00000
-; GCN-DAG: v_mov_b32_e32 v[[LOW_REG:[0-9]+]], [[CONSTREG]]
 ; GCN: buffer_store_dwordx4 v{{\[}}[[LOW_REG]]:
 define amdgpu_kernel void @insertelement_v4f32_0(<4 x float> addrspace(1)* %out, <4 x float> %a) nounwind {
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Given those are check-DAG, why do we have to update them?


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Comment at: llvm/test/CodeGen/AMDGPU/llvm.amdgcn.class.ll:15
+; SI: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, vcc
+; SI: buffer_store_dword [[RESULT]]
 ; SI: s_endpgm
----------------
Why do we need to weaken those checks?


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Comment at: llvm/test/CodeGen/X86/pr39391.ll:2
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc %s -O2 -mtriple=i686-unknown-linux-gnu -o - | FileCheck %s
+
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Could you give a more meaningful name to the file?
Put the PR number in the comments here.


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Comment at: llvm/test/CodeGen/X86/pr39391.ll:36
+  %d.h.h.h.h.h = bitcast i8* %0 to i64*
+  %2 = load atomic i64, i64* %d.h.h.h.h.h monotonic, align 8
+  %j.h = icmp eq i8 %1, 0
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Could you get rid of the implicit variables ([0-9]+)?
Use `opt -instnamer` for that.


Repository:
  rL LLVM

https://reviews.llvm.org/D54218