[PATCH] D54471: [SelectionDAG] Support differing src and dst alignments for memcpy/memmove

Nikita Popov via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue Nov 13 06:39:08 PST 2018


nikic created this revision.
Herald added subscribers: llvm-commits, jsji, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, atanasyan, mgrang, edward-jones, zzheng, jrtc27, niosHD, sabuasal, apazos, simoncook, johnrusso, rbar, asb, fedor.sergeev, kbarton, aheejin, jgravelle-google, sbc100, javed.absar, nhaehnle, jvesely, nemanjai, sdardis, jyknight, dschuff, arsenm.

The IR layer has already been switched to support different source and destination alignments for memcpy and memmove. However, this information is currently being discarded during SelectionDAG construction.

This patch pulls the different alignments through SelectionDAG and target lowering. The main changes are:

- `SelectionDAG::getMemcpy` and `SelectionDAG::getMemmove` now take separate `DstAlign` and `SrcAlign` arguments.
- `EmitTargetCodeForMemcpy` and `EmitTargetCodeForMemmove` now take separate `DstAlign` and `SrcAlign` arguments.
- Call-sites of `getMemcpy` are adjusted: These are usually either handling of byval arguments, or va_copy. In both cases I'm using the same source and destination alignment.
- Reviewed definitions of `getOptimalMemOpType` to make sure they treat the `DstAlign` and `SrcAlign` arguments correctly. These arguments were already separate previously, but there was a guarantee that always `SrcAlign >= DstAlign` (or zero). This guarantee no longer exists, so some additional checks need to be added.
- Added a test that shows mixed use of movaps/movups on X86 after this change. Previously all instructions were movups in the test.


Repository:
  rL LLVM

https://reviews.llvm.org/D54471

Files:
  include/llvm/CodeGen/SelectionDAG.h
  include/llvm/CodeGen/SelectionDAGTargetInfo.h
  lib/CodeGen/SelectionDAG/SelectionDAG.cpp
  lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
  lib/Target/AArch64/AArch64ISelLowering.cpp
  lib/Target/AMDGPU/SIISelLowering.cpp
  lib/Target/ARC/ARCISelLowering.cpp
  lib/Target/ARM/ARMSelectionDAGInfo.cpp
  lib/Target/ARM/ARMSelectionDAGInfo.h
  lib/Target/BPF/BPFSelectionDAGInfo.cpp
  lib/Target/BPF/BPFSelectionDAGInfo.h
  lib/Target/Hexagon/HexagonISelLowering.cpp
  lib/Target/Hexagon/HexagonSelectionDAGInfo.cpp
  lib/Target/Hexagon/HexagonSelectionDAGInfo.h
  lib/Target/Lanai/LanaiISelLowering.cpp
  lib/Target/Lanai/LanaiSelectionDAGInfo.cpp
  lib/Target/Lanai/LanaiSelectionDAGInfo.h
  lib/Target/MSP430/MSP430ISelLowering.cpp
  lib/Target/Mips/MipsISelLowering.cpp
  lib/Target/PowerPC/PPCISelLowering.cpp
  lib/Target/RISCV/RISCVISelLowering.cpp
  lib/Target/Sparc/SparcISelLowering.cpp
  lib/Target/SystemZ/SystemZISelLowering.cpp
  lib/Target/SystemZ/SystemZSelectionDAGInfo.cpp
  lib/Target/SystemZ/SystemZSelectionDAGInfo.h
  lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
  lib/Target/X86/X86ISelLowering.cpp
  lib/Target/X86/X86SelectionDAGInfo.cpp
  lib/Target/X86/X86SelectionDAGInfo.h
  lib/Target/XCore/XCoreISelLowering.cpp
  lib/Target/XCore/XCoreSelectionDAGInfo.cpp
  lib/Target/XCore/XCoreSelectionDAGInfo.h
  test/CodeGen/X86/memcpy-different-align.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D54471.173837.patch
Type: text/x-patch
Size: 47928 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20181113/7d4f868b/attachment-0001.bin>


More information about the llvm-commits mailing list