[llvm] r346594 - [InstCombine] auto-generate full checks; NFC
Sanjay Patel via llvm-commits
llvm-commits at lists.llvm.org
Sat Nov 10 10:51:10 PST 2018
Author: spatel
Date: Sat Nov 10 10:51:10 2018
New Revision: 346594
URL: http://llvm.org/viewvc/llvm-project?rev=346594&view=rev
Log:
[InstCombine] auto-generate full checks; NFC
Modified:
llvm/trunk/test/Transforms/InstCombine/load.ll
llvm/trunk/test/Transforms/InstCombine/store.ll
Modified: llvm/trunk/test/Transforms/InstCombine/load.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/load.ll?rev=346594&r1=346593&r2=346594&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/load.ll (original)
+++ llvm/trunk/test/Transforms/InstCombine/load.ll Sat Nov 10 10:51:10 2018
@@ -1,8 +1,7 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -instcombine -S < %s | FileCheck %s
; RUN: opt -passes=instcombine -S < %s | FileCheck %s
-; This test makes sure that these instructions are properly eliminated.
-
target datalayout = "e-m:e-p:64:64:64-i64:64-f80:128-n8:16:32:64-S128"
@X = constant i32 42 ; <i32*> [#uses=2]
@@ -13,99 +12,125 @@ target datalayout = "e-m:e-p:64:64:64-i6
@GLOBAL = internal constant [4 x i32] zeroinitializer
-; CHECK-LABEL: @test1(
-; CHECK-NOT: load
define i32 @test1() {
- %B = load i32, i32* @X ; <i32> [#uses=1]
- ret i32 %B
+; CHECK-LABEL: @test1(
+; CHECK-NEXT: ret i32 42
+;
+ %B = load i32, i32* @X ; <i32> [#uses=1]
+ ret i32 %B
}
-; CHECK-LABEL: @test2(
-; CHECK-NOT: load
define float @test2() {
- %A = getelementptr [2 x { i32, float }], [2 x { i32, float }]* @Y, i64 0, i64 1, i32 1 ; <float*> [#uses=1]
- %B = load float, float* %A ; <float> [#uses=1]
- ret float %B
+; CHECK-LABEL: @test2(
+; CHECK-NEXT: ret float 0x3FF3B2FEC0000000
+;
+ %A = getelementptr [2 x { i32, float }], [2 x { i32, float }]* @Y, i64 0, i64 1, i32 1 ; <float*> [#uses=1]
+ %B = load float, float* %A ; <float> [#uses=1]
+ ret float %B
}
-; CHECK-LABEL: @test3(
-; CHECK-NOT: load
define i32 @test3() {
- %A = getelementptr [2 x { i32, float }], [2 x { i32, float }]* @Y, i64 0, i64 0, i32 0 ; <i32*> [#uses=1]
- %B = load i32, i32* %A ; <i32> [#uses=1]
- ret i32 %B
+; CHECK-LABEL: @test3(
+; CHECK-NEXT: ret i32 12
+;
+ %A = getelementptr [2 x { i32, float }], [2 x { i32, float }]* @Y, i64 0, i64 0, i32 0 ; <i32*> [#uses=1]
+ %B = load i32, i32* %A ; <i32> [#uses=1]
+ ret i32 %B
}
-; CHECK-LABEL: @test4(
-; CHECK-NOT: load
define i32 @test4() {
- %A = getelementptr [2 x { i32, float }], [2 x { i32, float }]* @Z, i64 0, i64 1, i32 0 ; <i32*> [#uses=1]
- %B = load i32, i32* %A ; <i32> [#uses=1]
- ret i32 %B
+; CHECK-LABEL: @test4(
+; CHECK-NEXT: ret i32 0
+;
+ %A = getelementptr [2 x { i32, float }], [2 x { i32, float }]* @Z, i64 0, i64 1, i32 0 ; <i32*> [#uses=1]
+ %B = load i32, i32* %A ; <i32> [#uses=1]
+ ret i32 %B
}
-; CHECK-LABEL: @test5(
-; CHECK-NOT: load
define i32 @test5(i1 %C) {
- %Y = select i1 %C, i32* @X, i32* @X2 ; <i32*> [#uses=1]
- %Z = load i32, i32* %Y ; <i32> [#uses=1]
- ret i32 %Z
+; CHECK-LABEL: @test5(
+; CHECK-NEXT: [[Z:%.*]] = select i1 [[C:%.*]], i32 42, i32 47
+; CHECK-NEXT: ret i32 [[Z]]
+;
+ %Y = select i1 %C, i32* @X, i32* @X2 ; <i32*> [#uses=1]
+ %Z = load i32, i32* %Y ; <i32> [#uses=1]
+ ret i32 %Z
}
-; CHECK-LABEL: @test7(
-; CHECK-NOT: load
define i32 @test7(i32 %X) {
- %V = getelementptr i32, i32* null, i32 %X ; <i32*> [#uses=1]
- %R = load i32, i32* %V ; <i32> [#uses=1]
- ret i32 %R
+; CHECK-LABEL: @test7(
+; CHECK-NEXT: store i32 undef, i32* null, align 536870912
+; CHECK-NEXT: ret i32 undef
+;
+ %V = getelementptr i32, i32* null, i32 %X ; <i32*> [#uses=1]
+ %R = load i32, i32* %V ; <i32> [#uses=1]
+ ret i32 %R
}
-; CHECK-LABEL: @test7_no_null_opt(
-; CHECK: %V = getelementptr i32, i32* null
-; CHECK: %R = load i32, i32* %V
define i32 @test7_no_null_opt(i32 %X) #0 {
- %V = getelementptr i32, i32* null, i32 %X ; <i32*> [#uses=1]
- %R = load i32, i32* %V ; <i32> [#uses=1]
- ret i32 %R
+; CHECK-LABEL: @test7_no_null_opt(
+; CHECK-NEXT: [[TMP1:%.*]] = sext i32 [[X:%.*]] to i64
+; CHECK-NEXT: [[V:%.*]] = getelementptr i32, i32* null, i64 [[TMP1]]
+; CHECK-NEXT: [[R:%.*]] = load i32, i32* [[V]], align 4
+; CHECK-NEXT: ret i32 [[R]]
+;
+ %V = getelementptr i32, i32* null, i32 %X ; <i32*> [#uses=1]
+ %R = load i32, i32* %V ; <i32> [#uses=1]
+ ret i32 %R
}
attributes #0 = { "null-pointer-is-valid"="true" }
-; CHECK-LABEL: @test8(
-; CHECK-NOT: load
define i32 @test8(i32* %P) {
- store i32 1, i32* %P
- %X = load i32, i32* %P ; <i32> [#uses=1]
- ret i32 %X
+; CHECK-LABEL: @test8(
+; CHECK-NEXT: store i32 1, i32* [[P:%.*]], align 4
+; CHECK-NEXT: ret i32 1
+;
+ store i32 1, i32* %P
+ %X = load i32, i32* %P ; <i32> [#uses=1]
+ ret i32 %X
}
-; CHECK-LABEL: @test9(
-; CHECK-NOT: load
define i32 @test9(i32* %P) {
- %X = load i32, i32* %P ; <i32> [#uses=1]
- %Y = load i32, i32* %P ; <i32> [#uses=1]
- %Z = sub i32 %X, %Y ; <i32> [#uses=1]
- ret i32 %Z
+; CHECK-LABEL: @test9(
+; CHECK-NEXT: ret i32 0
+;
+ %X = load i32, i32* %P ; <i32> [#uses=1]
+ %Y = load i32, i32* %P ; <i32> [#uses=1]
+ %Z = sub i32 %X, %Y ; <i32> [#uses=1]
+ ret i32 %Z
}
-; CHECK-LABEL: @test10(
-; CHECK-NOT: load
define i32 @test10(i1 %C.upgrd.1, i32* %P, i32* %Q) {
- br i1 %C.upgrd.1, label %T, label %F
+; CHECK-LABEL: @test10(
+; CHECK-NEXT: br i1 [[C_UPGRD_1:%.*]], label [[T:%.*]], label [[F:%.*]]
+; CHECK: T:
+; CHECK-NEXT: store i32 1, i32* [[Q:%.*]], align 4
+; CHECK-NEXT: br label [[C:%.*]]
+; CHECK: F:
+; CHECK-NEXT: br label [[C]]
+; CHECK: C:
+; CHECK-NEXT: store i32 0, i32* [[P:%.*]], align 4
+; CHECK-NEXT: ret i32 0
+;
+ br i1 %C.upgrd.1, label %T, label %F
T: ; preds = %0
- store i32 1, i32* %Q
- store i32 0, i32* %P
- br label %C
+ store i32 1, i32* %Q
+ store i32 0, i32* %P
+ br label %C
F: ; preds = %0
- store i32 0, i32* %P
- br label %C
+ store i32 0, i32* %P
+ br label %C
C: ; preds = %F, %T
- %V = load i32, i32* %P ; <i32> [#uses=1]
- ret i32 %V
+ %V = load i32, i32* %P ; <i32> [#uses=1]
+ ret i32 %V
}
-; CHECK-LABEL: @test11(
-; CHECK-NOT: load
define double @test11(double* %p) {
+; CHECK-LABEL: @test11(
+; CHECK-NEXT: [[T0:%.*]] = getelementptr double, double* [[P:%.*]], i64 1
+; CHECK-NEXT: store double 2.000000e+00, double* [[T0]], align 8
+; CHECK-NEXT: ret double 2.000000e+00
+;
%t0 = getelementptr double, double* %p, i32 1
store double 2.0, double* %t0
%t1 = getelementptr double, double* %p, i32 1
@@ -113,9 +138,10 @@ define double @test11(double* %p) {
ret double %x
}
-; CHECK-LABEL: @test12(
-; CHECK-NOT: load
define i32 @test12(i32* %P) {
+; CHECK-LABEL: @test12(
+; CHECK-NEXT: ret i32 123
+;
%A = alloca i32
store i32 123, i32* %A
; Cast the result of the load not the source
@@ -124,22 +150,29 @@ define i32 @test12(i32* %P) {
ret i32 %V
}
-; CHECK-LABEL: @test13(
-; CHECK-NOT: load
define <16 x i8> @test13(<2 x i64> %x) {
+; CHECK-LABEL: @test13(
+; CHECK-NEXT: ret <16 x i8> zeroinitializer
+;
%tmp = load <16 x i8>, <16 x i8>* bitcast ([4 x i32]* @GLOBAL to <16 x i8>*)
ret <16 x i8> %tmp
}
-define i8 @test14(i8 %x, i32 %y) {
; This test must not have the store of %x forwarded to the load -- there is an
; intervening store if %y. However, the intervening store occurs with a different
; type and size and to a different pointer value. This is ensuring that none of
; those confuse the analysis into thinking that the second store does not alias
; the first.
+
+define i8 @test14(i8 %x, i32 %y) {
; CHECK-LABEL: @test14(
-; CHECK: %[[R:.*]] = load i8, i8*
-; CHECK-NEXT: ret i8 %[[R]]
+; CHECK-NEXT: [[A:%.*]] = alloca i32, align 4
+; CHECK-NEXT: [[A_I8:%.*]] = bitcast i32* [[A]] to i8*
+; CHECK-NEXT: store i8 [[X:%.*]], i8* [[A_I8]], align 4
+; CHECK-NEXT: store i32 [[Y:%.*]], i32* [[A]], align 4
+; CHECK-NEXT: [[R:%.*]] = load i8, i8* [[A_I8]], align 4
+; CHECK-NEXT: ret i8 [[R]]
+;
%a = alloca i32
%a.i8 = bitcast i32* %a to i8*
store i8 %x, i8* %a.i8
@@ -150,11 +183,15 @@ define i8 @test14(i8 %x, i32 %y) {
@test15_global = external global i32
-define i8 @test15(i8 %x, i32 %y) {
; Same test as @test14 essentially, but using a global instead of an alloca.
+
+define i8 @test15(i8 %x, i32 %y) {
; CHECK-LABEL: @test15(
-; CHECK: %[[R:.*]] = load i8, i8*
-; CHECK-NEXT: ret i8 %[[R]]
+; CHECK-NEXT: store i8 [[X:%.*]], i8* bitcast (i32* @test15_global to i8*), align 4
+; CHECK-NEXT: store i32 [[Y:%.*]], i32* @test15_global, align 4
+; CHECK-NEXT: [[R:%.*]] = load i8, i8* bitcast (i32* @test15_global to i8*), align 4
+; CHECK-NEXT: ret i8 [[R]]
+;
%g.i8 = bitcast i32* @test15_global to i8*
store i8 %x, i8* %g.i8
store i32 %y, i32* @test15_global
@@ -162,22 +199,26 @@ define i8 @test15(i8 %x, i32 %y) {
ret i8 %r
}
-define void @test16(i8* %x, i8* %a, i8* %b, i8* %c) {
; Check that we canonicalize loads which are only stored to use integer types
; when there is a valid integer type.
-; CHECK-LABEL: @test16(
-; CHECK: %[[L1:.*]] = load i32, i32*
-; CHECK-NOT: load
-; CHECK: store i32 %[[L1]], i32*
-; CHECK: store i32 %[[L1]], i32*
-; CHECK-NOT: store
-; CHECK: %[[L1:.*]] = load i32, i32*
-; CHECK-NOT: load
-; CHECK: store i32 %[[L1]], i32*
-; CHECK: store i32 %[[L1]], i32*
-; CHECK-NOT: store
-; CHECK: ret
+define void @test16(i8* %x, i8* %a, i8* %b, i8* %c) {
+; CHECK-LABEL: @test16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[C_CAST:%.*]] = bitcast i8* [[C:%.*]] to i32*
+; CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[X:%.*]] to i32*
+; CHECK-NEXT: [[X11:%.*]] = load i32, i32* [[TMP0]], align 4
+; CHECK-NEXT: [[TMP1:%.*]] = bitcast i8* [[A:%.*]] to i32*
+; CHECK-NEXT: store i32 [[X11]], i32* [[TMP1]], align 4
+; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8* [[B:%.*]] to i32*
+; CHECK-NEXT: store i32 [[X11]], i32* [[TMP2]], align 4
+; CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[X]] to i32*
+; CHECK-NEXT: [[X22:%.*]] = load i32, i32* [[TMP3]], align 4
+; CHECK-NEXT: [[TMP4:%.*]] = bitcast i8* [[B]] to i32*
+; CHECK-NEXT: store i32 [[X22]], i32* [[TMP4]], align 4
+; CHECK-NEXT: store i32 [[X22]], i32* [[C_CAST]], align 4
+; CHECK-NEXT: ret void
+;
entry:
%x.cast = bitcast i8* %x to float*
%a.cast = bitcast i8* %a to float*
@@ -196,15 +237,17 @@ entry:
ret void
}
-define void @test17(i8** %x, i8 %y) {
; Check that in cases similar to @test16 we don't try to rewrite a load when
; its only use is a store but it is used as the pointer to that store rather
; than the value.
-;
-; CHECK-LABEL: @test17(
-; CHECK: %[[L:.*]] = load i8*, i8**
-; CHECK: store i8 %y, i8* %[[L]]
+define void @test17(i8** %x, i8 %y) {
+; CHECK-LABEL: @test17(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[X_LOAD:%.*]] = load i8*, i8** [[X:%.*]], align 8
+; CHECK-NEXT: store i8 [[Y:%.*]], i8* [[X_LOAD]], align 1
+; CHECK-NEXT: ret void
+;
entry:
%x.load = load i8*, i8** %x
store i8 %y, i8* %x.load
@@ -214,13 +257,19 @@ entry:
; Check that we don't try change the type of the load by inserting a bitcast
; generating invalid IR.
-; CHECK-LABEL: @test18(
-; CHECK-NOT: bitcast
-; CHECK: ret
%swift.error = type opaque
declare void @useSwiftError(%swift.error** swifterror)
define void @test18(%swift.error** swifterror %err) {
+; CHECK-LABEL: @test18(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[SWIFTERROR:%.*]] = alloca swifterror %swift.error*, align 8
+; CHECK-NEXT: store %swift.error* null, %swift.error** [[SWIFTERROR]], align 8
+; CHECK-NEXT: call void @useSwiftError(%swift.error** nonnull swifterror [[SWIFTERROR]])
+; CHECK-NEXT: [[ERR_RES:%.*]] = load %swift.error*, %swift.error** [[SWIFTERROR]], align 8
+; CHECK-NEXT: store %swift.error* [[ERR_RES]], %swift.error** [[ERR:%.*]], align 8
+; CHECK-NEXT: ret void
+;
entry:
%swifterror = alloca swifterror %swift.error*, align 8
store %swift.error* null, %swift.error** %swifterror, align 8
@@ -231,15 +280,18 @@ entry:
}
; Make sure we preseve the type of the store to a swifterror pointer.
-; CHECK-LABEL: @test19(
-; CHECK: [[A:%.*]] = alloca
-; CHECK: call
-; CHECK: [[BC:%.*]] = bitcast i8** [[A]] to
-; CHECK: [[ERRVAL:%.*]] = load {{.*}}[[BC]]
-; CHECK: store {{.*}}[[ERRVAL]]
-; CHECK: ret
+
declare void @initi8(i8**)
define void @test19(%swift.error** swifterror %err) {
+; CHECK-LABEL: @test19(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP:%.*]] = alloca i8*, align 8
+; CHECK-NEXT: call void @initi8(i8** nonnull [[TMP]])
+; CHECK-NEXT: [[SWIFTERROR:%.*]] = bitcast i8** [[TMP]] to %swift.error**
+; CHECK-NEXT: [[ERR_RES:%.*]] = load %swift.error*, %swift.error** [[SWIFTERROR]], align 8
+; CHECK-NEXT: store %swift.error* [[ERR_RES]], %swift.error** [[ERR:%.*]], align 8
+; CHECK-NEXT: ret void
+;
entry:
%tmp = alloca i8*, align 8
call void @initi8(i8** %tmp)
Modified: llvm/trunk/test/Transforms/InstCombine/store.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/store.ll?rev=346594&r1=346593&r2=346594&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/store.ll (original)
+++ llvm/trunk/test/Transforms/InstCombine/store.ll Sat Nov 10 10:51:10 2018
@@ -1,40 +1,48 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -instcombine -S | FileCheck %s
define void @test1(i32* %P) {
- store i32 undef, i32* %P
- store i32 123, i32* undef
- store i32 124, i32* null
- ret void
; CHECK-LABEL: @test1(
-; CHECK-NEXT: store i32 123, i32* undef
-; CHECK-NEXT: store i32 undef, i32* null
-; CHECK-NEXT: ret void
+; CHECK-NEXT: store i32 123, i32* undef, align 4
+; CHECK-NEXT: store i32 undef, i32* null, align 536870912
+; CHECK-NEXT: ret void
+;
+ store i32 undef, i32* %P
+ store i32 123, i32* undef
+ store i32 124, i32* null
+ ret void
}
define void @test2(i32* %P) {
- %X = load i32, i32* %P ; <i32> [#uses=1]
- %Y = add i32 %X, 0 ; <i32> [#uses=1]
- store i32 %Y, i32* %P
- ret void
; CHECK-LABEL: @test2(
-; CHECK-NEXT: ret void
+; CHECK-NEXT: ret void
+;
+ %X = load i32, i32* %P
+ %Y = add i32 %X, 0
+ store i32 %Y, i32* %P
+ ret void
}
define void @store_at_gep_off_null(i64 %offset) {
-; CHECK-LABEL: @store_at_gep_off_null
-; CHECK: store i32 undef, i32* %ptr
- %ptr = getelementptr i32, i32 *null, i64 %offset
- store i32 24, i32* %ptr
- ret void
+; CHECK-LABEL: @store_at_gep_off_null(
+; CHECK-NEXT: [[PTR:%.*]] = getelementptr i32, i32* null, i64 [[OFFSET:%.*]]
+; CHECK-NEXT: store i32 undef, i32* [[PTR]], align 4
+; CHECK-NEXT: ret void
+;
+ %ptr = getelementptr i32, i32 *null, i64 %offset
+ store i32 24, i32* %ptr
+ ret void
}
define void @store_at_gep_off_no_null_opt(i64 %offset) #0 {
- %ptr = getelementptr i32, i32 *null, i64 %offset
- store i32 24, i32* %ptr
- ret void
-; CHECK-LABEL: @store_at_gep_off_no_null_opt(i64 %offset)
-; CHECK-NEXT: %ptr = getelementptr i32, i32* null, i64 %offset
-; CHECK-NEXT: store i32 24, i32* %ptr
+; CHECK-LABEL: @store_at_gep_off_no_null_opt(
+; CHECK-NEXT: [[PTR:%.*]] = getelementptr i32, i32* null, i64 [[OFFSET:%.*]]
+; CHECK-NEXT: store i32 24, i32* [[PTR]], align 4
+; CHECK-NEXT: ret void
+;
+ %ptr = getelementptr i32, i32 *null, i64 %offset
+ store i32 24, i32* %ptr
+ ret void
}
attributes #0 = { "null-pointer-is-valid"="true" }
@@ -43,79 +51,109 @@ attributes #0 = { "null-pointer-is-valid
; "if then else"
define i32 @test3(i1 %C) {
- %A = alloca i32
- br i1 %C, label %Cond, label %Cond2
+; CHECK-LABEL: @test3(
+; CHECK-NEXT: br i1 [[C:%.*]], label [[COND:%.*]], label [[COND2:%.*]]
+; CHECK: Cond:
+; CHECK-NEXT: br label [[CONT:%.*]]
+; CHECK: Cond2:
+; CHECK-NEXT: br label [[CONT]]
+; CHECK: Cont:
+; CHECK-NEXT: [[STOREMERGE:%.*]] = phi i32 [ -987654321, [[COND]] ], [ 47, [[COND2]] ]
+; CHECK-NEXT: ret i32 [[STOREMERGE]]
+;
+ %A = alloca i32
+ br i1 %C, label %Cond, label %Cond2
Cond:
- store i32 -987654321, i32* %A
- br label %Cont
+ store i32 -987654321, i32* %A
+ br label %Cont
Cond2:
- store i32 47, i32* %A
- br label %Cont
+ store i32 47, i32* %A
+ br label %Cont
Cont:
- %V = load i32, i32* %A
- ret i32 %V
-; CHECK-LABEL: @test3(
-; CHECK-NOT: alloca
-; CHECK: Cont:
-; CHECK-NEXT: %storemerge = phi i32 [ -987654321, %Cond ], [ 47, %Cond2 ]
-; CHECK-NEXT: ret i32 %storemerge
+ %V = load i32, i32* %A
+ ret i32 %V
}
; "if then"
define i32 @test4(i1 %C) {
- %A = alloca i32
- store i32 47, i32* %A
- br i1 %C, label %Cond, label %Cont
+; CHECK-LABEL: @test4(
+; CHECK-NEXT: br i1 [[C:%.*]], label [[COND:%.*]], label [[CONT:%.*]]
+; CHECK: Cond:
+; CHECK-NEXT: br label [[CONT]]
+; CHECK: Cont:
+; CHECK-NEXT: [[STOREMERGE:%.*]] = phi i32 [ -987654321, [[COND]] ], [ 47, [[TMP0:%.*]] ]
+; CHECK-NEXT: ret i32 [[STOREMERGE]]
+;
+ %A = alloca i32
+ store i32 47, i32* %A
+ br i1 %C, label %Cond, label %Cont
Cond:
- store i32 -987654321, i32* %A
- br label %Cont
+ store i32 -987654321, i32* %A
+ br label %Cont
Cont:
- %V = load i32, i32* %A
- ret i32 %V
-; CHECK-LABEL: @test4(
-; CHECK-NOT: alloca
-; CHECK: Cont:
-; CHECK-NEXT: %storemerge = phi i32 [ -987654321, %Cond ], [ 47, %0 ]
-; CHECK-NEXT: ret i32 %storemerge
+ %V = load i32, i32* %A
+ ret i32 %V
}
; "if then"
define void @test5(i1 %C, i32* %P) {
- store i32 47, i32* %P, align 1
- br i1 %C, label %Cond, label %Cont
+; CHECK-LABEL: @test5(
+; CHECK-NEXT: br i1 [[C:%.*]], label [[COND:%.*]], label [[CONT:%.*]]
+; CHECK: Cond:
+; CHECK-NEXT: br label [[CONT]]
+; CHECK: Cont:
+; CHECK-NEXT: [[STOREMERGE:%.*]] = phi i32 [ -987654321, [[COND]] ], [ 47, [[TMP0:%.*]] ]
+; CHECK-NEXT: store i32 [[STOREMERGE]], i32* [[P:%.*]], align 1
+; CHECK-NEXT: ret void
+;
+ store i32 47, i32* %P, align 1
+ br i1 %C, label %Cond, label %Cont
Cond:
- store i32 -987654321, i32* %P, align 1
- br label %Cont
+ store i32 -987654321, i32* %P, align 1
+ br label %Cont
Cont:
- ret void
-; CHECK-LABEL: @test5(
-; CHECK: Cont:
-; CHECK-NEXT: %storemerge = phi i32
-; CHECK-NEXT: store i32 %storemerge, i32* %P, align 1
-; CHECK-NEXT: ret void
+ ret void
}
; PR14753 - merging two stores should preserve the TBAA tag.
define void @test6(i32 %n, float* %a, i32* %gi) nounwind uwtable ssp {
+; CHECK-LABEL: @test6(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br label [[FOR_COND:%.*]]
+; CHECK: for.cond:
+; CHECK-NEXT: [[STOREMERGE:%.*]] = phi i32 [ 42, [[ENTRY:%.*]] ], [ [[INC:%.*]], [[FOR_BODY:%.*]] ]
+; CHECK-NEXT: store i32 [[STOREMERGE]], i32* [[GI:%.*]], align 4, !tbaa !0
+; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[STOREMERGE]], [[N:%.*]]
+; CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY]], label [[FOR_END:%.*]]
+; CHECK: for.body:
+; CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[STOREMERGE]] to i64
+; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[A:%.*]], i64 [[IDXPROM]]
+; CHECK-NEXT: store float 0.000000e+00, float* [[ARRAYIDX]], align 4, !tbaa !4
+; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[GI]], align 4, !tbaa !0
+; CHECK-NEXT: [[INC]] = add nsw i32 [[TMP0]], 1
+; CHECK-NEXT: br label [[FOR_COND]]
+; CHECK: for.end:
+; CHECK-NEXT: ret void
+;
entry:
store i32 42, i32* %gi, align 4, !tbaa !0
br label %for.cond
-for.cond: ; preds = %for.body, %entry
+for.cond:
%storemerge = phi i32 [ 0, %entry ], [ %inc, %for.body ]
%0 = load i32, i32* %gi, align 4, !tbaa !0
%cmp = icmp slt i32 %0, %n
br i1 %cmp, label %for.body, label %for.end
-for.body: ; preds = %for.cond
+for.body:
%idxprom = sext i32 %0 to i64
%arrayidx = getelementptr inbounds float, float* %a, i64 %idxprom
store float 0.000000e+00, float* %arrayidx, align 4, !tbaa !3
@@ -124,122 +162,130 @@ for.body:
store i32 %inc, i32* %gi, align 4, !tbaa !0
br label %for.cond
-for.end: ; preds = %for.cond
+for.end:
ret void
-; CHECK-LABEL: @test6(
-; CHECK: for.cond:
-; CHECK-NEXT: phi i32 [ 42
-; CHECK-NEXT: store i32 %storemerge, i32* %gi, align 4, !tbaa !0
}
define void @dse1(i32* %p) {
-; CHECK-LABEL: dse1
-; CHECK-NEXT: store
-; CHECK-NEXT: ret
+; CHECK-LABEL: @dse1(
+; CHECK-NEXT: store i32 0, i32* [[P:%.*]], align 4
+; CHECK-NEXT: ret void
+;
store i32 0, i32* %p
store i32 0, i32* %p
ret void
-}
+}
; Slightly subtle: if we're mixing atomic and non-atomic access to the
; same location, then the contents of the location are undefined if there's
-; an actual race. As such, we're free to pick either store under the
+; an actual race. As such, we're free to pick either store under the
; assumption that we're not racing with any other thread.
define void @dse2(i32* %p) {
-; CHECK-LABEL: dse2
-; CHECK-NEXT: store i32 0, i32* %p
-; CHECK-NEXT: ret
+; CHECK-LABEL: @dse2(
+; CHECK-NEXT: store i32 0, i32* [[P:%.*]], align 4
+; CHECK-NEXT: ret void
+;
store atomic i32 0, i32* %p unordered, align 4
store i32 0, i32* %p
ret void
-}
+}
define void @dse3(i32* %p) {
-; CHECK-LABEL: dse3
-; CHECK-NEXT: store atomic i32 0, i32* %p unordered, align 4
-; CHECK-NEXT: ret
+; CHECK-LABEL: @dse3(
+; CHECK-NEXT: store atomic i32 0, i32* [[P:%.*]] unordered, align 4
+; CHECK-NEXT: ret void
+;
store i32 0, i32* %p
store atomic i32 0, i32* %p unordered, align 4
ret void
-}
+}
define void @dse4(i32* %p) {
-; CHECK-LABEL: dse4
-; CHECK-NEXT: store atomic i32 0, i32* %p unordered, align 4
-; CHECK-NEXT: ret
+; CHECK-LABEL: @dse4(
+; CHECK-NEXT: store atomic i32 0, i32* [[P:%.*]] unordered, align 4
+; CHECK-NEXT: ret void
+;
store atomic i32 0, i32* %p unordered, align 4
store atomic i32 0, i32* %p unordered, align 4
ret void
-}
+}
; Implementation limit - could remove unordered store here, but
; currently don't.
define void @dse5(i32* %p) {
-; CHECK-LABEL: dse5
-; CHECK-NEXT: store
-; CHECK-NEXT: store
-; CHECK-NEXT: ret
+; CHECK-LABEL: @dse5(
+; CHECK-NEXT: store atomic i32 0, i32* [[P:%.*]] unordered, align 4
+; CHECK-NEXT: store atomic i32 0, i32* [[P]] seq_cst, align 4
+; CHECK-NEXT: ret void
+;
store atomic i32 0, i32* %p unordered, align 4
store atomic i32 0, i32* %p seq_cst, align 4
ret void
}
define void @write_back1(i32* %p) {
-; CHECK-LABEL: write_back1
-; CHECK-NEXT: ret
+; CHECK-LABEL: @write_back1(
+; CHECK-NEXT: ret void
+;
%v = load i32, i32* %p
store i32 %v, i32* %p
ret void
-}
+}
define void @write_back2(i32* %p) {
-; CHECK-LABEL: write_back2
-; CHECK-NEXT: ret
+; CHECK-LABEL: @write_back2(
+; CHECK-NEXT: ret void
+;
%v = load atomic i32, i32* %p unordered, align 4
store i32 %v, i32* %p
ret void
-}
+}
define void @write_back3(i32* %p) {
-; CHECK-LABEL: write_back3
-; CHECK-NEXT: ret
+; CHECK-LABEL: @write_back3(
+; CHECK-NEXT: ret void
+;
%v = load i32, i32* %p
store atomic i32 %v, i32* %p unordered, align 4
ret void
-}
+}
define void @write_back4(i32* %p) {
-; CHECK-LABEL: write_back4
-; CHECK-NEXT: ret
+; CHECK-LABEL: @write_back4(
+; CHECK-NEXT: ret void
+;
%v = load atomic i32, i32* %p unordered, align 4
store atomic i32 %v, i32* %p unordered, align 4
ret void
-}
+}
; Can't remove store due to ordering side effect
define void @write_back5(i32* %p) {
-; CHECK-LABEL: write_back5
-; CHECK-NEXT: load
-; CHECK-NEXT: store
-; CHECK-NEXT: ret
+; CHECK-LABEL: @write_back5(
+; CHECK-NEXT: [[V:%.*]] = load atomic i32, i32* [[P:%.*]] unordered, align 4
+; CHECK-NEXT: store atomic i32 [[V]], i32* [[P]] seq_cst, align 4
+; CHECK-NEXT: ret void
+;
%v = load atomic i32, i32* %p unordered, align 4
store atomic i32 %v, i32* %p seq_cst, align 4
ret void
}
define void @write_back6(i32* %p) {
-; CHECK-LABEL: write_back6
-; CHECK-NEXT: load
-; CHECK-NEXT: ret
+; CHECK-LABEL: @write_back6(
+; CHECK-NEXT: [[V:%.*]] = load atomic i32, i32* [[P:%.*]] seq_cst, align 4
+; CHECK-NEXT: ret void
+;
%v = load atomic i32, i32* %p seq_cst, align 4
store atomic i32 %v, i32* %p unordered, align 4
ret void
}
define void @write_back7(i32* %p) {
-; CHECK-LABEL: write_back7
-; CHECK-NEXT: load
-; CHECK-NEXT: ret
+; CHECK-LABEL: @write_back7(
+; CHECK-NEXT: [[V:%.*]] = load atomic volatile i32, i32* [[P:%.*]] seq_cst, align 4
+; CHECK-NEXT: ret void
+;
%v = load atomic volatile i32, i32* %p seq_cst, align 4
store atomic i32 %v, i32* %p unordered, align 4
ret void
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