[llvm] r346565 - [AVR] Reorder the CHECK lines in directmem.ll to match current trunk

[Dylan McKay via llvm-commits]

Author: dylanmckay
Date: Fri Nov  9 15:17:59 2018
New Revision: 346565

URL: http://llvm.org/viewvc/llvm-project?rev=346565&view=rev
Log:
[AVR] Reorder the CHECK lines in directmem.ll to match current trunk

In r346432 ("[DAGCombine] Improve alias analysis for chain of independent stores"),
the order of ldi/sts blocks changed.

The new IR is equivalent to the old IR.

This patch updates the test to fix the test suite.

Modified:
    llvm/trunk/test/CodeGen/AVR/directmem.ll

Modified: llvm/trunk/test/CodeGen/AVR/directmem.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/directmem.ll?rev=346565&r1=346564&r2=346565&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/directmem.ll (original)
+++ llvm/trunk/test/CodeGen/AVR/directmem.ll Fri Nov  9 15:17:59 2018
@@ -84,6 +84,11 @@ define i16 @global16_load() {
 define void @array16_store() {
 ; CHECK-LABEL: array16_store:
 
+; CHECK: ldi [[REG1:r[0-9]+]], 221
+; CHECK: ldi [[REG2:r[0-9]+]], 170
+; CHECK: sts int.array+5, [[REG2]]
+; CHECK: sts int.array+4, [[REG1]]
+
 ; CHECK: ldi [[REG1:r[0-9]+]], 204
 ; CHECK: ldi [[REG2:r[0-9]+]], 170
 ; CHECK: sts int.array+3, [[REG2]]
@@ -93,12 +98,6 @@ define void @array16_store() {
 ; CHECK: ldi [[REG2:r[0-9]+]], 170
 ; CHECK: sts int.array+1, [[REG2]]
 ; CHECK: sts int.array, [[REG1]]
-
-
-; CHECK: ldi [[REG1:r[0-9]+]], 221
-; CHECK: ldi [[REG2:r[0-9]+]], 170
-; CHECK: sts int.array+5, [[REG2]]
-; CHECK: sts int.array+4, [[REG1]]
   store i16 43707, i16* getelementptr inbounds ([3 x i16], [3 x i16]* @int.array, i32 0, i64 0)
   store i16 43724, i16* getelementptr inbounds ([3 x i16], [3 x i16]* @int.array, i32 0, i64 1)
   store i16 43741, i16* getelementptr inbounds ([3 x i16], [3 x i16]* @int.array, i32 0, i64 2)
@@ -152,30 +151,36 @@ define i32 @global32_load() {
 
 define void @array32_store() {
 ; CHECK-LABEL: array32_store:
+
+; CHECK: ldi [[REG1:r[0-9]+]], 170
+; CHECK: ldi [[REG2:r[0-9]+]], 153
+; CHECK: sts long.array+11, [[REG2]]
+; CHECK: sts long.array+10, [[REG1]]
+
+; CHECK: ldi [[REG1:r[0-9]+]], 204
+; CHECK: ldi [[REG2:r[0-9]+]], 187
+; CHECK: sts long.array+9, [[REG2]]
+; CHECK: sts long.array+8, [[REG1]]
+
 ; CHECK: ldi [[REG1:r[0-9]+]], 102
 ; CHECK: ldi [[REG2:r[0-9]+]], 85
 ; CHECK: sts long.array+7, [[REG2]]
 ; CHECK: sts long.array+6, [[REG1]]
+
 ; CHECK: ldi [[REG1:r[0-9]+]], 136
 ; CHECK: ldi [[REG2:r[0-9]+]], 119
 ; CHECK: sts long.array+5, [[REG2]]
 ; CHECK: sts long.array+4, [[REG1]]
+
 ; CHECK: ldi [[REG1:r[0-9]+]], 27
 ; CHECK: ldi [[REG2:r[0-9]+]], 172
 ; CHECK: sts long.array+3, [[REG2]]
 ; CHECK: sts long.array+2, [[REG1]]
+
 ; CHECK: ldi [[REG1:r[0-9]+]], 68
 ; CHECK: ldi [[REG2:r[0-9]+]], 13
 ; CHECK: sts long.array+1, [[REG2]]
 ; CHECK: sts long.array, [[REG1]]
-; CHECK: ldi [[REG1:r[0-9]+]], 170
-; CHECK: ldi [[REG2:r[0-9]+]], 153
-; CHECK: sts long.array+11, [[REG2]]
-; CHECK: sts long.array+10, [[REG1]]
-; CHECK: ldi [[REG1:r[0-9]+]], 204
-; CHECK: ldi [[REG2:r[0-9]+]], 187
-; CHECK: sts long.array+9, [[REG2]]
-; CHECK: sts long.array+8, [[REG1]]
   store i32 2887454020, i32* getelementptr inbounds ([3 x i32], [3 x i32]* @long.array, i32 0, i64 0)
   store i32 1432778632, i32* getelementptr inbounds ([3 x i32], [3 x i32]* @long.array, i32 0, i64 1)
   store i32 2578103244, i32* getelementptr inbounds ([3 x i32], [3 x i32]* @long.array, i32 0, i64 2)