[PATCH] D54093: [RISCV] Lower inline asm constraints I, J & K for RISC-V

[Lewis Revill via Phabricator via llvm-commits]

lewis-revill updated this revision to Diff 173300.
lewis-revill added a comment.

Use the register 'zero' for integer zero operands.


Repository:
  rL LLVM

https://reviews.llvm.org/D54093

Files:
  lib/Target/RISCV/RISCVISelLowering.cpp
  lib/Target/RISCV/RISCVISelLowering.h
  test/CodeGen/RISCV/inline-asm.ll

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